Design of a 7-segment decoder, with 4-bit reversible digital counter [specific requirements] 1. 7-segment decoder using the DIP switch SW3, SW2, SW1, SW0 as input, SW3 is high, SW0 is low. Will output the results in HEX1, HEX0 display. When the input is 0000 - 1111 is displayed as 00 to 15, (2) with a reversible 4-bit digital counter to the results of experiment 3 in the digital tube display. With previous experiments, the four reversible counters, digital display, respectively, as two sub-modules, to achieve the digital display on the 4-bit reversible counter.

V3(2)\cnt.vhd
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