VHDL-FPGA-Verilog List Page 1832

VHDL-FPGA-Verilog list

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Telephone_Book_27_06_17_48 Downloaded：0: Electronic telephone book on Altera DE1
Date : 2025-09-17 Size : 366kb User : yakov
Block-cipher Downloaded：0: block cipher encryption code
Date : 2025-09-17 Size : 7kb User : gaeib
I2C_9883_60 Downloaded：0: I2C Configuration program, the state machine
Date : 2025-09-17 Size : 2kb User : 陈翠莹
division-verilog Downloaded：0: The article introduced with sep Verilog HDL language writing any times frequency and the odd points even points of the principle and the frequency source program, through the simulation, the result completely correct.
Date : 2025-09-17 Size : 6kb User : 范先龙
FIFO-verilog Downloaded：0: Two asynchronous FIFO design and source code (Verilog)
Date : 2025-09-17 Size : 12kb User : 范先龙
EDA-experiments-based-on-VHDL Downloaded：0: The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
Date : 2025-09-17 Size : 4kb User : shi xin
EDA-principle_VHDL Downloaded：0: The file contains the courses of VHDL which can be applied to curriculum on college--EDA principle
Date : 2025-09-17 Size : 6.93mb User : shi xin
MD5Transform Downloaded：0: a MD5 encoder designed by me.It s a learning code for FPGA learner
Date : 2025-09-17 Size : 13.82mb User : Gevy
SHIZHONG Downloaded：0: This my own doing an electronic clock, with four digital control, microcontroller Hetai
Date : 2025-09-17 Size : 12kb User : 王太刚
rmfilter Downloaded：0: VHDL language with the best achieved by the receiver filter
Date : 2025-09-17 Size : 1kb User : 筱雲
pingpang Downloaded：0: in the development of FPGA, implement jointless link of data by tow external SRAM.
Date : 2025-09-17 Size : 4kb User : baihuachun
async_transmitter Downloaded：0: failed to translate
Date : 2025-09-17 Size : 1kb User : 韩小

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