VHDL-FPGA-Verilog List Page 1830

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .25 .26 .27 .28 .29 1830.31 .32 .33 .34 .35 ... 4310 »

usb1_funct_latest.tar Downloaded：1: USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in h
Date : 2025-09-17 Size : 58kb User : Andrey
Isis Downloaded：0: ISIS LCD Serial RS232
Date : 2025-09-17 Size : 23kb User : Hatem
lect-4 Downloaded：0: these slides for digital logic design
Date : 2025-09-17 Size : 905kb User : fahad
lect-1(prt-1) Downloaded：0: slides of vhdl first chapter
Date : 2025-09-17 Size : 2.29mb User : fahad
lect-2a[3] Downloaded：0: slides of vhdl chap no 2
Date : 2025-09-17 Size : 1.93mb User : fahad
EDA-fenpinqi Downloaded：0: Multi-level divider graphic design, frequency input frequency of 10 MHz, the output frequency of 1 Hz. Divider top-level design of graphics files, for example, graphics files of the module design.
Date : 2025-09-17 Size : 33kb User : 范骏
Asynchronous-FIFO-Design Downloaded：0: Asynchronous FIFO design,including six modules.HDL language is verilog.
Date : 2025-09-17 Size : 3kb User : 林峰
e_pro_restored Downloaded：0: 2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
Date : 2025-09-17 Size : 4.05mb User : 郭冰冰
b_pro3_restored Downloaded：0: 2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
Date : 2025-09-17 Size : 7.33mb User : 郭冰冰
interpolation-filer-rtl Downloaded：0: synthesizable verilog rtl implemetation of interpolation filter, for both asic and fpga. 64x interpolation. interp_filter.v interp_first.v interp_second.v interp_third.v upsample.v
Date : 2025-09-17 Size : 3kb User : swordever
EP3C8020111219125810_ROM_OK5 Downloaded：0: Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct. This routine is very simple and clear, as DSP builder of the Getting Started Sample
Date : 2025-09-17 Size : 13.27mb User : 刘洋
lfsr Downloaded：0: simple PRBS generator using verilog hdl
Date : 2025-09-17 Size : 1kb User : karthik

« 1 2 ... .25 .26 .27 .28 .29 1830.31 .32 .33 .34 .35 ... 4310 »

Search in result