VHDL-FPGA-Verilog List Page 1713

VHDL-FPGA-Verilog list

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i2c_controller Downloaded：0: The Verilog language implementation the I2C master controller example, testing program
Date : 2025-09-15 Size : 1.89mb User : wu
can_controller Downloaded：0: CAN protocol controller examples, and the overall structure, modules realize, module testing
Date : 2025-09-15 Size : 1015kb User : wu
MEMCTRL Downloaded：0: Based on the works of the verilog storage controller chip design. Use the Quartus II 4.0 or later to open the design engineering documents.
Date : 2025-09-15 Size : 3.42mb User : fangcheng
RTP_h_264 Downloaded：0: The RTP protocol is given in RFC1889 by IETF (Internet Engineering TaskFo rce), light transmission protocol is designed specifically for interactive audio, video, simulation data and real-time media applications. RTP is
Date : 2025-09-15 Size : 114kb User : 李国
MIF_file_of_Sine_Wave_Generator Downloaded：0: Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to the desired data bits and the length of custom mif file.
Date : 2025-09-15 Size : 1kb User :
view_quartus_simu_on_matlab Downloaded：0: During Quartus simulation, waveform directly with their own simulation tools can not view the sine wave, Save the simulation data for the tbl format, using the Matlab program to call the tbl files, can be observed. Of co
Date : 2025-09-15 Size : 1kb User :
NCO Downloaded：0: IP cores in Quartus NCO design source files
Date : 2025-09-15 Size : 6.25mb User :
DIV_oddN Downloaded：0: Quartus development environment, the design of the universal fractional divider, to meet various needs.
Date : 2025-09-15 Size : 435kb User :
DDS Downloaded：0: Quartus environment, general DDS design using VHDL and IP cores.
Date : 2025-09-15 Size : 1.4mb User :
AVR-program Downloaded：0: ATmega 16 a variety of code containing AD converter AT24C02 I2C DS1302 EEPROM read and write PWMO control LED Button Timer 0 fast PWM Timer 0 phase correct PWM Timer 0 overflow Timer 1 capture Asynchronous serial UART Sy
Date : 2025-09-15 Size : 314kb User : 陈杰
code Downloaded：0: 5divider code， and easy to understand,you will find it is easy to write
Date : 2025-09-15 Size : 35kb User : 惠盼玲
FPGA1 Downloaded：0: Understand the importance of verilog modeling, development of FPGA to have the help very much.
Date : 2025-09-15 Size : 1.28mb User : ff

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