VHDL-FPGA-Verilog List Page 1715

VHDL-FPGA-Verilog list

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FSM_Recepcion Downloaded：0: Finite State Machine to receive data froma pc ina serial communication
Date : 2025-09-15 Size : 243kb User : banhallem
LFSR Downloaded：0: Linear Feedback Shift Register created to generate random numbers
Date : 2025-09-15 Size : 244kb User : banhallem
Prueba_RS232 Downloaded：0: Its only a schematic of probe to complete the sending of data through rs232
Date : 2025-09-15 Size : 536kb User : banhallem
RNG Downloaded：0: Random number Generator based in vhdl
Date : 2025-09-15 Size : 666kb User : banhallem
decoder_case Downloaded：0: verilog hdl program for decoder
Date : 2025-09-15 Size : 1kb User : Basanta Aryal
decoder_ca Downloaded：0: coder for different modules in verilog
Date : 2025-09-15 Size : 1kb User : Basanta Aryal
decoder Downloaded：0: coder for different modules in verilog
Date : 2025-09-15 Size : 2kb User : Basanta Aryal
decode Downloaded：0: codes for different modules in verilog
Date : 2025-09-15 Size : 2kb User : Basanta Aryal
decode12 Downloaded：0: codes for different modules in verilog
Date : 2025-09-15 Size : 3kb User : Basanta Aryal
decoder-and-encoder Downloaded：0: codes for different modules in verilog
Date : 2025-09-15 Size : 4kb User : Basanta Aryal
m-operand-n-bit-adder Downloaded：0: n bit m operand adder
Date : 2025-09-15 Size : 1kb User : isnehil
FPGA--design-and-example Downloaded：0: This book is the study of the FPGA classic books, including the basic knowledge of FPGA, and seven practical engineering examples in explanation,
Date : 2025-09-15 Size : 4.93mb User : hua

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