VHDL-FPGA-Verilog List Page 1708

VHDL-FPGA-Verilog list

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mpci32-verilog Downloaded：0: pci ipcore writen by verilog
Date : 2025-09-15 Size : 706kb User : 刘华
verilog-LCD126484 Downloaded：0: LCD12864 display program written with verilog HDL, allowing the LCD display
Date : 2025-09-15 Size : 383kb User : 黄浩
VHDL_project Downloaded：0: it is a very good way to study the fpga
Date : 2025-09-15 Size : 35kb User : 何阳
Temperature_acquisition Downloaded：0: 8-channel temperature data sampling function is implemented on FPGA using VHDL language. Control THS1408 chip AD converter, and sampled into the corresponding set of registers, and generate the enable signal to inform ot
Date : 2025-09-15 Size : 2kb User : 张明
stack Downloaded：0: Designed with a depth of 64, the word length is 16_bit stack, stack empty, stack full and stack overflow signal. Trial to the way of bi-directional shift register or memory structure of the circuit structure designed to
Date : 2025-09-15 Size : 371kb User : 张明
Analog_AD Downloaded：0: Data through the first stored in the ROM, the simulation of the code chip AD9942 timing, the ROM data as input, generate data after AD conversion
Date : 2025-09-15 Size : 6kb User : 张明
VHDL-VGA Downloaded：0: Based on the color bar signal VHDL VGA display controller, to achieve the preset image or animation function correctly displayed on a VGA monitor
Date : 2025-09-15 Size : 4kb User : JACK
VHDL-NoteTabs- Downloaded：0: Experimental NC divider hardware music played the circuit, the main system consists of three modules, top-level design file, within three functional modules, TONETABA.VHD NOTETABS.VHD, and SPEAKERA.VHD on the basis of th
Date : 2025-09-15 Size : 5kb User : JACK
Sinusoidal-signal-generator-design Downloaded：0: Sinusoidal signal generator design，Simple combinational circuit design, multi-level circuit design
Date : 2025-09-15 Size : 5kb User : JACK
RS232 Downloaded：0: The code based on RS232 protocol to send and receive data. The module can be ported to any FPGA that uses the protocol.
Date : 2025-09-15 Size : 3kb User : 张明
DDS-Based-on-VHDL Downloaded：0: Thesis and design of a hardware description language VHDL-based direct digital frequency synthesizer.
Date : 2025-09-15 Size : 1.68mb User : zhuimeng
EDK_exp Downloaded：0: EDK design example code of Xilinx ISE13.4
Date : 2025-09-15 Size : 11.5mb User : ah

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