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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 371kb
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  • Author :张***
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Introduction - If you have any usage issues, please Google them yourself
Designed with a depth of 64, the word length is 16_bit stack, stack empty, stack full and stack overflow signal. Trial to the way of bi-directional shift register or memory structure of the circuit structure designed to complete the circuit, and explain its characteristics.
Packet file list
(Preview for download)
adder_1b.v
adder_3b.v
bidirectreg_1_16b.v
bidirectreg_4_16b.v
mux_21_16b.v
mux_21_1b.v
outreg.v
stack.v
stack_tb.v
toppointer.v
模块设计说明.doc
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