VHDL-FPGA-Verilog List Page 1588

VHDL-FPGA-Verilog list

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sumUnit Downloaded：0: Convert result of binary adding to 3-digits BCD code, and thus make it easy to display the result with 7 segments decoders.
Date : 2025-09-13 Size : 1kb User : 文玖泽
IEEE802_16e Downloaded：0: intervel ieee802.1
Date : 2025-09-13 Size : 44kb User : yjl
i2c_con Downloaded：0: Simulation using FPGA I2C on the TVP5150AM1 chip configuration, belonging to a simple I2C application, using FPGA simulation, eliminating the hardware implementation of I2C, the work is simple.
Date : 2025-09-13 Size : 865kb User : hanbo
sdr_sdram Downloaded：0: Using FPGA realize SDRAM control, mainly the SDRAM timing out, this is very good do.
Date : 2025-09-13 Size : 2.45mb User : hanbo
123 Downloaded：0: State machine in the FPGA with the control of the digital control
Date : 2025-09-13 Size : 944kb User : 王得鑫
zaidaidankuaipaipinghua Downloaded：0: Narrowband signals and single-snapshot direction finding Improve the signal to noise ratio by smoothing
Date : 2025-09-13 Size : 1kb User : 聂玺
xapp378 Downloaded：0: Design of a NAND flash controller of AMD flash
Date : 2025-09-13 Size : 146kb User : Tian
test_tones Downloaded：0: quartus tone
Date : 2025-09-13 Size : 35kb User : 胡亚文
RAM Downloaded：0: Verilog dual port and single port RAM-based implementation
Date : 2025-09-13 Size : 134kb User : xinghe
vga Downloaded：0: Based verilog VGA design
Date : 2025-09-13 Size : 126kb User : xinghe
DDR-SDRAM Downloaded：0: The design of DDR SDRAM, DDR SDRAM controller, and Modelsim simulation
Date : 2025-09-13 Size : 876kb User : xinghe
Code_for_MedianFilter33 Downloaded：0: Numerical image processing: the median filter design, the design code of 3* 3 square window, edge detection
Date : 2025-09-13 Size : 53kb User : xinghe

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