VHDL-FPGA-Verilog List Page 1583

VHDL-FPGA-Verilog list

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DE2_70_TV_PIP Downloaded：0: The DE2 code, mainly related to the processing of the picture in picture, with a unique approach, it is worth learning from.
Date : 2025-09-13 Size : 362kb User : 庄辉
DE2_70_AUDIO Downloaded：0: DE2 of audio processing
Date : 2025-09-13 Size : 4.48mb User : 庄辉
FPGA_Programming Downloaded：0: Introduce the basic structure of the FPGA development process, and Verilog HDL language foundation, along with the adder, shift register code.
Date : 2025-09-13 Size : 367kb User : 王岱维
99-down-count Downloaded：0: 99 down counter
Date : 2025-09-13 Size : 1.51mb User : lisa
Example1 Downloaded：0: fifo verilog hdl along with test bench its hardware
Date : 2025-09-13 Size : 3kb User : zakirmj
Example1B Downloaded：0: verilog code with its test bench
Date : 2025-09-13 Size : 2kb User : zakirmj
Example2 Downloaded：0: this one also verilog source code with its test bench
Date : 2025-09-13 Size : 3kb User : zakirmj
Example2B Downloaded：0: this one also verilog code with its test bench
Date : 2025-09-13 Size : 2kb User : zakirmj
ROM-based-sine-wave-generator-of-the-design-the-u Downloaded：0: Rom based Sine wave generator
Date : 2025-09-13 Size : 1kb User : Ladik
Micro-SD Downloaded：0: Digital module will be a variety of extensions to the unified bus lead, then through the system control panel, connecting the corresponding peripheral interface, in order to realize the corresponding function
Date : 2025-09-13 Size : 11kb User : 刘坚胜
parallel-CRC-calculation-in-FPGAs- Downloaded：0: To introduce the crc check principle and algorithm。To achieve the description in fpga
Date : 2025-09-13 Size : 90kb User : 吴越强
A-Fast-CRC-Implementation-on-FPGA Downloaded：0: The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sofisticated implementations. In this paper, we present a method to
Date : 2025-09-13 Size : 221kb User : 吴越强

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