Verilog dual port and single port RAM-based implementation

dqram\db\altsyncram_vif1.tdf
.....\..\dual.db_info
.....\..\dual.sim.cvwf
.....\..\dual.sim.vwf
.....\..\prev_cmp_dual.asm.qmsg
.....\..\prev_cmp_dual.eda.qmsg
.....\..\prev_cmp_dual.fit.qmsg
.....\..\prev_cmp_dual.map.qmsg
.....\..\prev_cmp_dual.qmsg
.....\..\prev_cmp_dual.sim.qmsg
.....\..\prev_cmp_dual.tan.qmsg
.....\..\wed.wsf
.....\..\wed.zsf
.....\ddr_settings.dwz
.....\dual.asm.rpt
.....\dual.done
.....\dual.eda.rpt
.....\dual.fit.rpt
.....\dual.fit.smsg
.....\dual.fit.summary
.....\dual.flow.rpt
.....\dual.map.rpt
.....\dual.map.smsg
.....\dual.map.summary
.....\dual.pin
.....\dual.pof
.....\dual.qpf
.....\dual.qsf
.....\dual.qws
.....\dual.sim.rpt
.....\dual.sof
.....\dual.tan.rpt
.....\dual.tan.summary
.....\dual.v
.....\dual.v.bak
.....\dual.vwf
.....\dual_assignment_defaults.qdf
.....\dual_nativelink_simulation.rpt
.....\incremental_db\compiled_partitions\dual.db_info
.....\..............\...................\dual.root_partition.map.kpt
.....\..............\README
.....\RAM.v
.....\simulation\modelsim\dual.sft
.....\..........\........\dual.vo
.....\..........\........\dual_modelsim.xrf
.....\..........\........\dual_v.sdo
.pram\db\logic_util_heursitic.dat
.....\..\prev_cmp_reg_dpram.qmsg
.....\..\reg_dpram.db_info
.....\incremental_db\compiled_partitions\reg_dpram.db_info
.....\..............\README
.....\reg_dpram.asm.rpt
.....\reg_dpram.done
.....\reg_dpram.eda.rpt
.....\reg_dpram.fit.rpt
.....\reg_dpram.fit.smsg
.....\reg_dpram.fit.summary
.....\reg_dpram.flow.rpt
.....\reg_dpram.map.rpt
.....\reg_dpram.map.summary
.....\reg_dpram.pin
.....\reg_dpram.pof
.....\reg_dpram.qpf
.....\reg_dpram.qsf
.....\reg_dpram.sof
.....\reg_dpram.sta.rpt
.....\reg_dpram.sta.summary
.....\reg_dpram.v
.....\reg_dpram.v.bak
.....\reg_dpram_nativelink_simulation.rpt
.qram\incremental_db\compiled_partitions
.....\simulation\modelsim
.pram\incremental_db\compiled_partitions
.qram\db
.....\incremental_db
.....\simulation
.pram\db
.....\incremental_db
dqram
dpram

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