VHDL-FPGA-Verilog List Page 158

VHDL-FPGA-Verilog list

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design Downloaded：0: sequence detection with state mation
Date : 2025-08-17 Size : 158kb User : tc280
DATA_Scramble Downloaded：0: FPGA scrambler, scrambler specifications for a 15 bit shift register.
Date : 2025-08-17 Size : 31kb User : 菜菜0106
uart_rxd Downloaded：0: UART with Verilog, there are frequency divider module, can adjust the baud rate
Date : 2025-08-17 Size : 10.3mb User : zmxer
W5300_IF Downloaded：0: Fast Ethernet communication between FPGA and W5300 chip, the actual project in many applications
Date : 2025-08-17 Size : 4kb User : bug赵
dac_controller Downloaded：0: dac controller ip /dac controller
Date : 2025-08-17 Size : 2kb User : haohmf
Digital_Tube_Core Downloaded：0: Digital_Tube_Core/Digital_Tube ip
Date : 2025-08-17 Size : 3kb User : haohmf
RX_IP_Source Downloaded：0: uart receive TX_IP_Source
Date : 2025-08-17 Size : 12kb User : haohmf
TX_IP_Source Downloaded：0: uart transmit TX_IP_Source
Date : 2025-08-17 Size : 9kb User : haohmf
Verilog_HDL时序篇教程及代码 Downloaded：0: A good set of learning information for Verilog timing chapter, with source code and engineering documents, you can follow the tutorial self-study
Date : 2025-08-17 Size : 57.57mb User : UestcCoder
EightLEDSame Downloaded：0: Digital tube data shift display
Date : 2025-08-17 Size : 203kb User : 稷下
SRAM_OK Downloaded：0: SRAM configuration OV7620 frame cache
Date : 2025-08-17 Size : 12.61mb User : 寇梓黎
pudn Downloaded：0: Encoders, decoders and RAM Model
Date : 2025-08-17 Size : 11kb User : sheldon01

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