VHDL-FPGA-Verilog List Page 1518

VHDL-FPGA-Verilog list

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pingponggames Downloaded：0: Table tennis game design using VHDL language, complete the design requirements, as well as the realization of the complete code
Date : 2025-09-12 Size : 1018kb User : wjc
6 Downloaded：0: vhdl language implementation of the traffic lights, red light 18 seconds, yellow for 2 seconds, cyclic transformation of the four directions.
Date : 2025-09-12 Size : 313kb User : maidi
clock Downloaded：0: vhdl language to achieve clock quartus project. Can get the clock running on the FPGA results, and regulatory function.
Date : 2025-09-12 Size : 1.17mb User : maidi
verilog-code Downloaded：0: MUX code and REGISTER code clock divider code string conversion circuit code, Shannon extended op code, the ram code.
Date : 2025-09-12 Size : 2.33mb User : ponyma
vg Downloaded：0: By vhdl programming the vga display horizontal and vertical color bar code. And board barcode
Date : 2025-09-12 Size : 1kb User : sun
traffic Downloaded：0: DE2_traffic_light(in verilog source code)
Date : 2025-09-12 Size : 1kb User : Ercan Kerim
Matching Downloaded：0: In FPGA design, realize the matching between pins and buffers by finding the shortest path for all the pins.
Date : 2025-09-12 Size : 233kb User : angela
eda Downloaded：0: EDA development and design of the VHDL language description of the music sound
Date : 2025-09-12 Size : 718kb User : 李勋
Frequency-tester Downloaded：0: Digital frequency measurement，Can automatic testing input square wave pulse frequency, through the LCD1602 shows, it is to use Verilog HDL write
Date : 2025-09-12 Size : 8kb User : 豪哥
watch Downloaded：0: DE-2-based digital stopwatch design, with two display
Date : 2025-09-12 Size : 3kb User : chenzhiwei
AM_restored Downloaded：0: DDS sine signal generator can be used to generate sine signal modulation.
Date : 2025-09-12 Size : 637kb User : 刘文
time-of-clock Downloaded：0: dan pian ji zhong shi xian yige shi zhong de daim a
Date : 2025-09-12 Size : 39kb User : xiaoqiang

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