vhdl language implementation of the traffic lights, red light 18 seconds, yellow for 2 seconds, cyclic transformation of the four directions.

实验6\1.bmp
.....\2.bmp
.....\3.bmp
.....\4.bmp
.....\clock.bsf
.....\clock.vhd
.....\cmp_state.ini
.....\db\add_sub_e6b.tdf
.....\..\add_sub_f6b.tdf
.....\..\add_sub_g6b.tdf
.....\..\add_sub_ke8.tdf
.....\..\add_sub_le8.tdf
.....\..\add_sub_ma8.tdf
.....\..\add_sub_me8.tdf
.....\..\add_sub_na8.tdf
.....\..\add_sub_ne8.tdf
.....\..\add_sub_oe8.tdf
.....\..\add_sub_pe8.tdf
.....\..\alt_u_div_bld.tdf
.....\..\alt_u_div_dld.tdf
.....\..\alt_u_div_fld.tdf
.....\..\Design0.db_info
.....\..\Design0.eco.cdb
.....\..\Design0.sld_design_entry.sci
.....\..\Design0_cmp.qrpt
.....\..\lpm_divide_d7f.tdf
.....\..\lpm_divide_fve.tdf
.....\..\lpm_divide_hlf.tdf
.....\..\lpm_divide_kdf.tdf
.....\..\sign_div_unsign_e3g.tdf
.....\..\sign_div_unsign_f3g.tdf
.....\..\sign_div_unsign_jhg.tdf
.....\decode.bdf
.....\decode_ctrl.bdf
.....\Design.bdf
.....\Design0.asm.rpt
.....\Design0.bdf
.....\Design0.bsf
.....\Design0.cdf
.....\Design0.done
.....\Design0.fit.eqn
.....\Design0.fit.rpt
.....\Design0.fit.summary
.....\Design0.flow.rpt
.....\Design0.map.eqn
.....\Design0.map.rpt
.....\Design0.map.summary
.....\Design0.pin
.....\Design0.pof
.....\Design0.qpf
.....\Design0.qsf
.....\Design0.qws
.....\Design0.sof
.....\Design0.tan.rpt
.....\Design0.tan.summary
.....\Design0_assignment_defaults.qdf
.....\Design0_description.txt
.....\generator.vhd
.....\LEDrgy.bdf
.....\LEDr_0_1.bdf
.....\LEDr_2_3.bdf
.....\SEG0.bdf
.....\SEG1.bdf
.....\SEG2_1.bdf
.....\SEG2_2.bdf
.....\SINGLE_PULSE.bdf
.....\SW_0_1.bdf
.....\SW_0_2.bdf
.....\db
实验6

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