VHDL-FPGA-Verilog List Page 1516

VHDL-FPGA-Verilog list

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singen Downloaded：0: Using the VHDL in a QuartusII in the preparation of the sinusoidal signal generator, and makes simulation in Quartus
Date : 2025-09-12 Size : 539kb User : sunyanjuan
dds_wave Downloaded：0: Based on the digital frequency synthesis technology of DDS, written in QuartusII code, achieve sinusoidal signal output, and can achieve amplitude modulation, frequency modulation and digital tube.
Date : 2025-09-12 Size : 9.46mb User : sunyanjuan
RISC_CPU Downloaded：0: The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the st
Date : 2025-09-12 Size : 6kb User : 林琳
901_1 Downloaded：0: Which contains the Manchester encoding and decoding is probably described and written in Verilog code.
Date : 2025-09-12 Size : 1.7mb User : jim
USART Downloaded：0: RS232 serial communication VERILOG code contains the test files and parameter files, users only need to modify the parameters in the parameter file to meet different application requirements serial logic is relatively si
Date : 2025-09-12 Size : 4kb User : chendongkui
clock Downloaded：0: In Quartus II environment developed a multi-function digital clock, is a complete project, including the simulation and programming download files.
Date : 2025-09-12 Size : 498kb User :
FPGAMp3Player_MihaiAndreiVeres Downloaded：0: MP3 player, and SD card SPI mode interaction, as well as file system using VHDL
Date : 2025-09-12 Size : 1.84mb User : 赵抟
dc-motor-speed-control Downloaded：0: Pwm dc motor speed control based on VHDL
Date : 2025-09-12 Size : 349kb User : ganun
dds Downloaded：0: Dds engineering documents, write your own used VHDl, triangle wave, square wave. Positive sine wave
Date : 2025-09-12 Size : 1.15mb User : chen
VerilogHDL Downloaded：0: More detailed description of the the verilonghdl language, is a rare books
Date : 2025-09-12 Size : 10.36mb User : chenhao
Verilog16-bit-counter-design Downloaded：0: Verilog16 bit counter design, simple 16-digit calculation.
Date : 2025-09-12 Size : 1kb User : 陈俊辉
D-flip-flop Downloaded：0: Simple D flip-flop in Verilog design
Date : 2025-09-12 Size : 1kb User : 陈俊辉

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