VHDL-FPGA-Verilog List Page 149

VHDL-FPGA-Verilog list

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systemc-2.2.0 Downloaded：0: System C 2.2.0 developers file
Date : 2025-05-19 Size : 11.57mb User : alexandr210186
新建 WinRAR ZIP 压缩文件 Downloaded：0: Asynchronous FIFO and I2C bus controller for cross clock domain data transmission.
Date : 2025-05-19 Size : 290kb User : 打好额速度
5.c Downloaded：0: ; for 16-bit app support [386Enh] woafont=dosapp.fon EGA80WOA.FON=EGA80WOA.FON EGA40WOA.FON=EGA40WOA.FON CGA80WOA.FON=CGA80WOA.FON CGA40WOA.FON=CGA40WOA.FON
Date : 2025-05-19 Size : 2kb User : fov120
uart Downloaded：0: The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached
Date : 2025-05-19 Size : 301kb User : 怪了个乖
CPU_16bit Downloaded：0: A five section of the 16 bit CPU VHDL source code, can be integrated can also be simulated
Date : 2025-05-19 Size : 3.25mb User : sunrihui
lattice_usb_ft2232_cable_sch Downloaded：0: Lattice USB FT2232 JTAG Programming Cable Schematic
Date : 2025-05-19 Size : 237kb User : kaos_engr
Double_Pulse_Test Downloaded：0: A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.
Date : 2025-05-19 Size : 7.93mb User : 张子铭
lcd Downloaded：0: copy of hello word on FPGA
Date : 2025-05-19 Size : 186kb User : kentucky
cic3s32 Downloaded：0: The 3 order CIC filter, 16 bit output, 32 fold down sampling processing
Date : 2025-05-19 Size : 1kb User : today_ztt
sincos Downloaded：0: sine wave generator by using verilog
Date : 2025-05-19 Size : 756kb User : zhangchaoruo
avs_aes_latest Downloaded：0: This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
Date : 2025-05-19 Size : 1.29mb User : rajban
ODriveFPGA-master Downloaded：0: Motor control by using FPGA
Date : 2025-05-19 Size : 185kb User : zhangchaoruo

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