VHDL-FPGA-Verilog List Page 1460

VHDL-FPGA-Verilog list

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counter Downloaded：0: 16-bit addition and subtraction controller based on the hexadecimal subtraction
Date : 2026-01-23 Size : 36kb User : 顶顶顶
sinw Downloaded：0: Sine wave generator written in Verilog
Date : 2026-01-23 Size : 509kb User : 杀虫剂
verilog_rtl Downloaded：0: EXPLANATION FOR SERIAL COMMUNICATION
Date : 2026-01-23 Size : 107kb User : MOHSIN
ADC Downloaded：0: AVR microcontroller ADC conversion function, detailed notes for beginners
Date : 2026-01-23 Size : 1kb User : ling
fredivn Downloaded：0: Divider VHDL code and simulation code on the ISE development board
Date : 2026-01-23 Size : 1kb User : 徐汉杰
mult_16 Downloaded：0: Three 16-digit sum of the multiplier Verilog
Date : 2026-01-23 Size : 1kb User : 吴雪红
uart Downloaded：0: Verilog VHDL the uart of the DE2
Date : 2026-01-23 Size : 495kb User : jakeli
dianzibiao Downloaded：0: module clock(clk,rst,clock_en,second,minute,hour) input clk,rst,clock_en output[5:0]second,minute,hour reg[5:0]second,minute,hour
Date : 2026-01-23 Size : 109kb User : dianzibiao
Attachments_2012_06_19 Downloaded：0: verilog basic materials
Date : 2026-01-23 Size : 471kb User : Regina
FPGA-development--and-VHDL--based Downloaded：0: FPGA development process and VHDL language based
Date : 2026-01-23 Size : 479kb User : lhxiao
8.8_FPGA Downloaded：0: Described briefly Universal Asynchronous Receiver Transmitter design, some detail may be less clear
Date : 2026-01-23 Size : 89kb User : 王杰
pinlvji Downloaded：0: Use verilog language, design a three decimal digital frequency meter
Date : 2026-01-23 Size : 2.58mb User : dengchunlei

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