VHDL-FPGA-Verilog List Page 1465

VHDL-FPGA-Verilog list

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The-simulation-led Downloaded：0: The simulation led to the dot matrix display, bright and dark and then cycle you entered
Date : 2025-09-11 Size : 19kb User : 董文武
BasysRevEBist Downloaded：0: kind of digital WaveGenerator and Oscilloscope based on tne BASYS experiment board which has a Xilinx Spartan-3E FPGA on it.This design can make adjustable sine,triangle and rectangle waveform.It also can show the wavef
Date : 2025-09-11 Size : 1.19mb User : 赵志彪
AIC23_Configure_Test Downloaded：0: Verilog to write about AIC23 configuration program, the board has been verified.
Date : 2025-09-11 Size : 427kb User : 张亚洲
6bit_cymometer Downloaded：0: 89C51 series microcontroller to achieve the significant frequency of the 6-digit counter (including simulation files)
Date : 2025-09-11 Size : 48kb User : 黄志健
UniformRNG Downloaded：0: A Uniform Random Number Generator in VHDL
Date : 2025-09-11 Size : 1kb User : Vahid
shft_reg_8_vhdl Downloaded：0: this a shift register vhdl code
Date : 2025-09-11 Size : 1kb User : yz
AD_change Downloaded：0: Use ADC0809 analog and digital conversion, digital tube display the actual data, tested the precision measurement of analog data with the actual voltmeter
Date : 2025-09-11 Size : 487kb User : 崔可
duoji_pwm Downloaded：0: A simple program to control the servo, tested can also facilitate
Date : 2025-09-11 Size : 570kb User : 崔可
verilog Downloaded：0: Verilog 中文教學 1.簡介 2. Verilog 的模型 3. Verilog 的架構 4. MAX+plus II 的環境 5. 基本資料型態 6. 輸出入埠的宣告 7. 邏輯閘階層模型的敘述 8. 資料流模型的敘述 9. 行為模型的敘述 10. 編譯命令 11. 循序邏輯電路範例
Date : 2025-09-11 Size : 586kb User : bill
loopback Downloaded：0: Xilinx FPGAs to achieve the 68013 usb transfer
Date : 2025-09-11 Size : 386kb User : NOOW
askfsk Downloaded：0: Communication theory ask, FSK simulation processes using max+plus achieve
Date : 2025-09-11 Size : 292kb User : lpx_matlab
MIPS-multi-cycle-(Quarters-II--Verillig) Downloaded：0: Multi cycle MIPS processor verilog
Date : 2025-09-11 Size : 2.12mb User : zzang1323

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