VHDL-FPGA-Verilog List Page 1445

VHDL-FPGA-Verilog list

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S2_counter Downloaded：0: In this study, digital development board above the pipe to achieve a decimal counter, counting range 0000-9999 cycle count.
Date : 2025-09-11 Size : 266kb User : luoyong
s4_music Downloaded：0: Music and the microprocessor (CPU or MCU) compared with pure hardware logic of the music circuit is relatively complex, without the help of the powerful EDA tools and hardware description languages, purely traditional di
Date : 2025-09-11 Size : 267kb User : luoyong
s5_led Downloaded：0: This experiment is the use of LED lights on the bottom plate, the cycle of the LED lamp is lit.
Date : 2025-09-11 Size : 145kb User : luoyong
decoder4_16 Downloaded：0: vhdl decoder4_16
Date : 2025-09-11 Size : 54kb User : zhang
adder_n Downloaded：0: This "adder_n".
Date : 2025-09-11 Size : 30kb User : zhang
number Downloaded：0: Vhdl language segment digital tube display to learn the number of procedures, equipment validation error-free, and a good run in Quartus
Date : 2025-09-11 Size : 279kb User : 李晶盈
DE2_TV Downloaded：0: display a music score via VGA and you can write the notes on the screen one by one with a PS2 keyboard on DE2.
Date : 2025-09-11 Size : 5.08mb User : hdm
ss868_FallingSandGame Downloaded：0: On the DE2, falling a game of various media, players by manipulating the keyboard to draw on the bezel, the screen will fall a variety of media materials, they will show the true physical properties.
Date : 2025-09-11 Size : 76kb User : hdm
DigiClock_v1.0 Downloaded：0: Multi-function digital clock: contains the default mode, setting mode, alarm mode and stopwatch mode. The source code has been successfully burned in ISE10.1 fpga board, which is a Xilinx Spartan 3 xc3s400 pq205 speed-4
Date : 2025-09-11 Size : 65kb User : triblade
sin_generate Downloaded：0: verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
Date : 2025-09-11 Size : 416kb User : 陈占田
ask-psk-qpsk Downloaded：0: ask, psk, qpsk debugging demodulator verilog source, is a wireless communications fpga design of this book, a relatively simple way to achieve
Date : 2025-09-11 Size : 5kb User : 陈占田
convertor Downloaded：0: Four BCD binary switch
Date : 2025-09-11 Size : 253kb User : 李晶盈

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