VHDL-FPGA-Verilog List Page 1438

VHDL-FPGA-Verilog list

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state_machine Downloaded：0: A VHDL implementation of FPGA-based simple state machine program
Date : 2025-09-11 Size : 195kb User : 阿虎
decimetion Downloaded：0: Save the character to upload the accumulation of many years of working code. The main function is to adc the multi-order follow-up digital filter control. Can be integrated.
Date : 2025-09-11 Size : 35kb User : fx10001
ddr_ctrl Downloaded：0: Save the character to upload the accumulation of many years of working code. The main function is to ddr memery controler interface control. Can be integrated.
Date : 2025-09-11 Size : 85kb User : fx10001
osd Downloaded：0: Save the character to upload the accumulation of many years of working code. The main function is to control the OSD graphics code. Proven, can be integrated.
Date : 2025-09-11 Size : 13kb User : fx10001
rgb2yuv Downloaded：0: Save the character to upload the accumulation of many years of working code. The main function of the RGB to YUV conversion code, you can chip integrated.
Date : 2025-09-11 Size : 66kb User : fx10001
vds_proc Downloaded：0: A well-known foreign companies lifted the verilog code. The main function is the video display processing and control. Can be integrated.
Date : 2025-09-11 Size : 26kb User : fx10001
infmt Downloaded：0: Save the character to upload the accumulation of many years of working code. The main function is to control video input signal filtering. Can be integrated.
Date : 2025-09-11 Size : 17kb User : fx10001
scaler Downloaded：0: Save the character to upload the accumulation of many years of working code. The main function is to deal with changes in size of the video signal format. Can be integrated.
Date : 2025-09-11 Size : 23kb User : fx10001
16mult_signed Downloaded：0: 16 x 16 signed multiplier verilog language
Date : 2025-09-11 Size : 1kb User : 371645042
dintlace Downloaded：0: The function of super-interlaced video signal transfer progressive filter Verilog code, after the fpga verification.
Date : 2025-09-11 Size : 82kb User : mmmm1111111111
fifo_ctrl Downloaded：0: Useful fifo control verilog source code for the study reference, can be integrated.
Date : 2025-09-11 Size : 6kb User : mmmm1111111111
firfilt Downloaded：0: FIR filter verilog source code, fpga verification can be integrated.
Date : 2025-09-11 Size : 5kb User : mmmm1111111111

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