VHDL-FPGA-Verilog List Page 1433

VHDL-FPGA-Verilog list

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fpq Downloaded：0: Fpga-based crossover design, the complete code and engineering
Date : 2025-09-10 Size : 2.18mb User :
ipfp Downloaded：0: Fpga-based crossover design, using the ip nuclear, complete engineering and code
Date : 2025-09-10 Size : 349kb User :
crc_tool Downloaded：0: Automatically generate the verilog code to parallel crc processing tools written with c
Date : 2025-09-10 Size : 55kb User : wangxin
prbs Downloaded：0: High-speed parallel pseudo-random data modules, including randomized and receive side of sending side to randomization, and the test module
Date : 2025-09-10 Size : 9kb User : wangxin
m_seq Downloaded：0: M sequence generator written in VHDL code, including the generator and the test case module
Date : 2025-09-10 Size : 2kb User : wangxin
agc Downloaded：0: Receive side of the AGC module vhdl code for wireless communications
Date : 2025-09-10 Size : 6kb User : wangxin
cic-1 Downloaded：0: cic filter decimation verilog code and testch
Date : 2025-09-10 Size : 2kb User : 黄远望
lms Downloaded：1: Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger summary
Date : 2025-09-10 Size : 2.68mb User : 黄远望
multiplier Downloaded：0: 8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
Date : 2025-09-10 Size : 2kb User :
EX28_CPLD Downloaded：0: The connection between DSP and CPLD
Date : 2025-09-10 Size : 197kb User :
multiplier Downloaded：0: 8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations
Date : 2025-09-10 Size : 2kb User :
add Downloaded：0: 16 of the adder, full adder and effective use of the gate for the binary full adder
Date : 2025-09-10 Size : 1kb User :

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