VHDL-FPGA-Verilog List Page 1367

VHDL-FPGA-Verilog list

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shuzizhong Downloaded：0: Use vhdl languages designed electronic clock. Has hours, minutes, seconds count and a 24-hour cycle timing. The timing results use six digital tube display hours, minutes, seconds, ten and a bit. Has a clear funct
Date : 2025-08-29 Size : 315kb User : 陈小龙
youpiao Downloaded：1: Using vhdl language design vending stamp machine. Sold two light-emitting diodes were simulated nominal value of 60 cents and 80 cents stamps, buyers can switch to select a face value of stamps sold stamps lights. Analog
Date : 2025-08-29 Size : 134kb User : 陈小龙
jiaotongdeng Downloaded：0: Using vhdl language design traffic lights. By a main road and a branch roads converge into a crossroads, and at each entrance red, green, yellow and white signal lights, red light is closed to traffic, the green light to
Date : 2025-08-29 Size : 56kb User : 陈小龙
watch Downloaded：0: Vhdl design digital display stopwatch accurate timing and display boot display 00.00.00 Users can be cleared at any time, suspend, timing 59 minutes maximum chronograph, accurate to 0.01 seconds minimum.
Date : 2025-08-29 Size : 338kb User : 陈小龙
lsd Downloaded：0: Light water using VHDL language, available through debugging, I hope you can learn from everyone.
Date : 2025-08-29 Size : 151kb User : 吴达
saomiao Downloaded：0: Determinant keyboard scanning procedures, already using VHDL language debugging can be helpful to students to use the keyboard.
Date : 2025-08-29 Size : 122kb User : 吴达
seg7_move Downloaded：0: Digital dynamic display using VHDL language program debugging has been available.
Date : 2025-08-29 Size : 126kb User : 吴达
ADV715 Downloaded：0: it is a vhdl code it is a vhdl codei t is a vhdl codei t is a vhdl codei t is a vhdl codei t is a vhdl code
Date : 2025-08-29 Size : 11kb User : comp
delay Downloaded：0: A delay procedures based on FPGA VHDL written.
Date : 2025-08-29 Size : 1kb User : wuqi
FIR Downloaded：1: Half-band interpolation filter cascade optimization sub-module design.
Date : 2025-08-29 Size : 24kb User : 陈凯
RS232 Downloaded：0: RS232 communication program and FPGA, QUARTUS II 7.1 test results, correct
Date : 2025-08-29 Size : 462kb User : zzy
baseband-code-generator-program Downloaded：0: The baseband code generator program design and simulation. Doc
Date : 2025-08-29 Size : 46kb User : 无名

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