VHDL-FPGA-Verilog List Page 1361

VHDL-FPGA-Verilog list

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VHDL Downloaded：0: The circuit consists of seven main modules: clock generation module is used to generate 1KHz scan clock and 1Hz clock frequency module for 1Hz clock signal frequency measurement/calibration selection module for function
Date : 2025-08-29 Size : 2kb User : 张骞
si_xi_fen Downloaded：0: Quartus environment, use verilog HDL write light code disc four segmentation procedure, are used to obtain steering and speed
Date : 2025-08-29 Size : 347kb User :
ad976 Downloaded：0: AD976 FPGA to realize the automatic sampling of the verilog HDL program, the is AD976 model a, already debugging succe
Date : 2025-08-29 Size : 528kb User :
ad976_CS Downloaded：0: AD976 FPGA to realize the automatic sampling of the Verilog HDL program, the AD976 is the mode 2, i.e., to use the CS signal, already debugging succe
Date : 2025-08-29 Size : 133kb User :
1602 Downloaded：0: VHDL realization of 1602 liquid crystal display program, already debugging succe
Date : 2025-08-29 Size : 213kb User :
RS232 Downloaded：0: VHDL realization of RS232 communication procedures, send and receive are realized
Date : 2025-08-29 Size : 196kb User :
Prentice---Verilog.HDL_A.Guide.to.Digital.Design. Downloaded：0: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspec
Date : 2025-08-29 Size : 1.64mb User : bom
SHA_1_V Downloaded：0: FIPS 180-4 standard SHA-1 algorithm-based verilog HDL implementation
Date : 2025-08-29 Size : 3kb User : pppp
SHA-256 Downloaded：0: SHA-256 algorithm based on FIPS 180-4 standard verilog HDL implementation
Date : 2025-08-29 Size : 4kb User : pppp
softdrink_testbench Downloaded：0: Verilog HDL description of a state machine used in vending machines
Date : 2025-08-29 Size : 1kb User : pppp
sha1_v01 Downloaded：0: FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve
Date : 2025-08-29 Size : 6kb User : pppp
quartus-clock.RAR Downloaded：0: Design FPGA circuits to analog the multifunctional electronic table work process, the following functions: (1) digital clock count: 00 points from 00:00 to 23: 59:59 (2) digital the stopwatch (3) to adjust the time (4 )
Date : 2025-08-29 Size : 1.59mb User : 章梓音

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