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VHDL-FPGA-Verilog list
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tanchishe
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verilog prepared by the Snake game, vga on display by sp3 keyboard to control the movement of the snake to eat the food
Date : 2025-08-29 Size : 20kb User :
EDA
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VHDL achieve a integral point time of the stopwatch 1
Date : 2025-08-29 Size : 6kb User : 于欣雨
comp_16
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Design 16-bit synchronous counter requirements: (1) analysis of the 16-bit synchronous counter and circuit characteristics (2) hardware description language design (3) preparation of test simulation and simulation.
Date : 2025-08-29 Size : 20kb User : 15416
sv
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stack and events in system verilog
Date : 2025-08-29 Size : 1kb User : Kiran
LCD-Driver-And-Keyboard-char-Asm(www.bargh20.com)
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LCD Driver And Keyboard char Asm(www.bargh20.com)
Date : 2025-08-29 Size : 20kb User : vahid
7_DynDigTub
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FPGA, VHDL language dynamically display a digital tube, all FPGA chip, the lesson reallocate pin! !
Date : 2025-08-29 Size : 415kb User : 李诚
2_KeyLED
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FPGA, VHDL language with the keys lit a lamp, applies to all FPGA chip and can reallocate pin! !
Date : 2025-08-29 Size : 272kb User : 李诚
6_DigTub
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FPGA, VHDL language static lit a digital control applies to all FPGA chip, VHDL source code!
Date : 2025-08-29 Size : 275kb User : 李诚
8_LigWater
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FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !
Date : 2025-08-29 Size : 443kb User : 李诚
9_TheBell
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FPGA, VHDL language buzzer 0.5S ~ ~, clock divider source, applicable to all FPGA chip! !
Date : 2025-08-29 Size : 372kb User : 李诚
1_Lit_OneLED
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FPGA, VHDL language, static light a LED VHDL source code ~ ~ ~ applies to all FPGA chip!
Date : 2025-08-29 Size : 269kb User : 李诚
Proj
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AD data is read, write CF card control, adjustable acquisition rate and storage rate
Date : 2025-08-29 Size : 1.5mb User : wang
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