VHDL-FPGA-Verilog List Page 1352

VHDL-FPGA-Verilog list

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fast-crc_latest.tar Downloaded：0: A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)
Date : 2025-08-29 Size : 4.55mb User : gollasantu
viterb_encoder_and_decoder_latest.tar Downloaded：0: Category: Arithmetic core Language: Verilog Development status: Mature Additional info: Design done, Specification done WishBone Compliant: No
Date : 2025-08-29 Size : 448kb User : gollasantu
fpu100_latest.tar Downloaded：0: Features - FPU supports the following arithmetic operations: - Add - Subtract - Multiply - Divide - Square Root
Date : 2025-08-29 Size : 1.88mb User : gollasantu
vdhl Downloaded：0: examples for VHDL
Date : 2025-08-29 Size : 292kb User : 王锋
VHDL--examples-and-answers Downloaded：0: Verilog HDL
Date : 2025-08-29 Size : 99kb User : 王锋
Example-8-1 Downloaded：0: Modular Design Example-8-1
Date : 2025-08-29 Size : 420kb User : 王锋
wallace Downloaded：0: wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications
Date : 2025-08-29 Size : 3kb User : ganesh
Verilog Downloaded：0: Verilog code routines, helpful for the beginner FPGA
Date : 2025-08-29 Size : 16.06mb User : nong
elevator Downloaded：0: Six-story elevator control, consistent with the actual logic of operation of the elevator opened the door automatically closed (Note: No quick closing and opening function 5s)
Date : 2025-08-29 Size : 766kb User : 樊旭
sd Downloaded：0: NIOS read images from SD card displayed on the TFT screen
Date : 2025-08-29 Size : 245kb User : 宇智波带土
onchip_seg Downloaded：0: NIOS FPGA on-chip memory nuclear 12345673564
Date : 2025-08-29 Size : 15.63mb User : 宇智波带土
sdram_seg Downloaded：0: Based on the NIOS the SDram nuclear.
Date : 2025-08-29 Size : 4.97mb User : 宇智波带土

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