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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 20kb
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  • Author :15***
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Design 16-bit synchronous counter requirements: (1) analysis of the 16-bit synchronous counter and circuit characteristics (2) hardware description language design (3) preparation of test simulation and simulation.
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transcript
work\_info
....\_vmake
....\comp_16_tb\_primary.vhd
....\.......\_primary.vhd
....\......._tb\verilog.asm
....\.......\verilog.asm
comp_16.v.bak
comp_16_tb.v.bak
work\comp_16\_primary.dbs
....\......._tb\_primary.dbs
comp_16.mpf
comp_16.cr.mti
work\comp_16_tb\verilog.rw
....\.......\verilog.rw
comp_16.v
comp_16_tb.v
vsim.wlf
work\comp_16\_primary.dat
....\......._tb\_primary.dat
....\_temp
....\comp_16_tb
....\comp_16
work
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