VHDL-FPGA-Verilog List Page 1307

VHDL-FPGA-Verilog list

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demo_2012_2 Downloaded：0: KD_CPU,8bit CPU with basic functions, base on verilog
Date : 2025-08-27 Size : 11kb User : Victor
code Downloaded：0: Five water CPU to perform division, logical shift, arithmetic shift and other advanced features
Date : 2025-08-27 Size : 11kb User : Victor
Dragon-Heart_VERILOG.doc Downloaded：0: The verilog design specification of BLX cpu
Date : 2025-08-27 Size : 65kb User : Victor
code_VHDL Downloaded：0: cpu code with no water nor cache
Date : 2025-08-27 Size : 10kb User : Victor
code-water-no-cache Downloaded：0: cpu code with no water nor cache
Date : 2025-08-27 Size : 12kb User : Victor
MULT Downloaded：0: With VERILOG multiplier function is verified by simulation
Date : 2025-08-27 Size : 395kb User : 蚩建峰
MUX_8 Downloaded：0: Serial communication program, is verified by simulation with verilog
Date : 2025-08-27 Size : 92kb User : 蚩建峰
add Downloaded：0: Adder verilog achieve program is verified by simulation
Date : 2025-08-27 Size : 211kb User : 蚩建峰
UART Downloaded：0: Serial communication program, is verified by simulation with verilog
Date : 2025-08-27 Size : 40kb User : 蚩建峰
pll Downloaded：0: Odd divider program is verified by simulation with verilog
Date : 2025-08-27 Size : 230kb User : 蚩建峰
digita_clock Downloaded：0: spartan 3 7 segment clock display
Date : 2025-08-27 Size : 4.12mb User : asra12
SAR_Send Downloaded：0: test of RS code and RS decode,by using quartus ii9.0 with the IP core
Date : 2025-08-27 Size : 11.72mb User : 蔡金平

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