VHDL-FPGA-Verilog List Page 1305

VHDL-FPGA-Verilog list

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Modelsim-setup Downloaded：0: VHDL development environment---- modelsim installation steps
Date : 2025-08-27 Size : 682kb User : 王子
Three-voting-machine Downloaded：0: Three voting machine
Date : 2025-08-27 Size : 35kb User : 王子
Four-bit-full-adder Downloaded：0: I have written four full adder, is subject to error, please forgive
Date : 2025-08-27 Size : 39kb User : 王子
ram Downloaded：0: CPU a part-- RAM programming, using FPGA, hardware description language
Date : 2025-08-27 Size : 2kb User : 回音男孩
picoblaze Downloaded：0: picoblaze top level entity for xilinx
Date : 2025-08-27 Size : 568kb User : nassim
xmtr Downloaded：0: VHDL UART SEND
Date : 2025-08-27 Size : 1kb User : 陈诚
Recv Downloaded：0: VHDL UART RECEIVE
Date : 2025-08-27 Size : 1kb User : 陈诚
AntGlitch Downloaded：0: The use of the VHDL language, to achieve the the pulse collected filtering subroutine utilize playing two beats glitch filtering, the sub module is loaded into the main program.
Date : 2025-08-27 Size : 1kb User : 陈诚
baud_gen Downloaded：0: VHDL language, set the baud rate of the serial transceiver subroutine, this sub-module is loaded into the main program.
Date : 2025-08-27 Size : 1kb User : 陈诚
switch Downloaded：0: The use of VHDL language the MAX7317' s acquisition program, this sub-module is loaded into the main program.
Date : 2025-08-27 Size : 1kb User : 陈诚
AD7793 Downloaded：1: VHDL language to achieve the AD7793 chip sampling procedures and SPI communication program, this sub-module is loaded into the main program.
Date : 2025-08-27 Size : 2kb User : 陈诚
adc Downloaded：0: The analog-to-digital conversion, the sampling frequency is 1/36 of the clock frequency, can be dual simultaneous sampling, as well as serial output, the output data 14 of the number of symbols.
Date : 2025-08-27 Size : 368kb User : zwl6600233

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