VHDL-FPGA-Verilog List Page 1301

VHDL-FPGA-Verilog list

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BUS_Control Downloaded：0: bus controller fpga bus_control control procedures, data acquisition, there will be very useful.
Date : 2025-08-27 Size : 1kb User : neal
spi Downloaded：0: The spi Timing control procedures. In fpga, data transmission, and will by spi master exchange spi part of this procedure is used in the data transmission timing control.
Date : 2025-08-27 Size : 1kb User : neal
DE2_CCD Downloaded：0: The DE2 board CCD camera and a VGA monitor, real-time face tracking, can be mobile as the face of the front and rear, VGA display different patterns of size
Date : 2025-08-27 Size : 255kb User : huoi
uart_rx Downloaded：0: acceptance uart communication module, serial communication uart need to record data from peripherals, acquisition and timing control, asynchronous transmission.
Date : 2025-08-27 Size : 1kb User : neal
uart_tx Downloaded：0: uart communication sending module, in the serial communication, the communication of the peripheral and send the corresponding instruction, and to adjust its timing logic.
Date : 2025-08-27 Size : 1kb User : neal
VGA Downloaded：0: Fpga driver vga, a total of two experiments, the code is fully functional and complete quartus open form of engineering
Date : 2025-08-27 Size : 811kb User : 宋
xiangwei_90 Downloaded：0: Generating a set of orthogonal carrier signals, multiplied by the applied chopper control, analog multiplier.
Date : 2025-08-27 Size : 69kb User : 游有鹏
Tx_state Downloaded：0: Used in real-time Ethernet communication, asynchronous clock domain communication speed FIFO FIFO operation state machine, with the physical layer chip communication.
Date : 2025-08-27 Size : 876kb User : 游有鹏
Multi-function-waveform-generator Downloaded：0: The system using VHDL language and MAX+ PLUS II simulation software using a top-down design ideas to design a combined oscilloscope be completed to do the input pulse signal or reference pulse signal with the signal gene
Date : 2025-08-27 Size : 1.42mb User : xinxing
tt_qsys_design Downloaded：0: Qsys Tutorial Design Example
Date : 2025-08-27 Size : 219kb User : renaifeng
tlc5620 Downloaded：0: TLC5620C with high input impedance buffer 4-channel 8 collection of power output digital-to-analog converter using fpga verilog description
Date : 2025-08-27 Size : 632kb User : 官雄辉
FPGA--SDRAM Downloaded：0: 同步动态随机存储器，同步是指 Memory工作需要同步时钟，内部的命令的发送与数据的传输都以它为基准；动态是指存储阵列需要不断的刷新来保证数据不丢失；随机是指数据不是线性依次存储，而是自由指定地址进行数据读写。
Date : 2025-08-27 Size : 19mb User : 官雄辉

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