VHDL-FPGA-Verilog List Page 1167

VHDL-FPGA-Verilog list

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REQUEST Downloaded：0: Request - Para Sensores
Date : 2025-08-21 Size : 328kb User : Fabiano Alves
Sensor Downloaded：0: Sensor de Temperatura
Date : 2025-08-21 Size : 24kb User : Fabiano Alves
Lightflu_cycle Downloaded：0: Verilog programming control procedures of the light water recirculating eight lights lit
Date : 2025-08-21 Size : 297kb User : 赵亮亮
VHDL_uart Downloaded：0: using xilinx s FPGA-spartan3E to implement uart with a baudrate of 9600, even parity check. The system frequency is 50MHz.It can turn the data from serial assistant in PC back to the PC
Date : 2025-08-21 Size : 714kb User : john
elevator-verilog-code Downloaded：0: SRAM CONTROLLER CAN GIVE YOU CORRET IDEA ABOUT VERILOG
Date : 2025-08-21 Size : 24kb User : DOSASPATRUNI SIVA
_12_DA[TLC5615]_1 Downloaded：0: DA output sine wave frequency 1KHz The ad is TLC5615 The sine wave output with the ideal waveform is basically the same
Date : 2025-08-21 Size : 2.85mb User : 江风
CPLD_AD_AVR Downloaded：0: The CPLD program, the program to achieve a PWM wave generation high-speed AD ADS8364 parallel read and write control, and communication control of the AVR microcontroller. CPLD manner similar to the external RAM read and
Date : 2025-08-21 Size : 4kb User : emouse
fenfshan Downloaded：0: Verilog control procedures of the fan, strong wind, low wind, sleep and other functions
Date : 2025-08-21 Size : 249kb User : luo
startup Downloaded：0: Spartan-3E starter development board entry routine re-compiled version, this version use the latest version ISE14.1 recompile. Added missing files, through the actual test.
Date : 2025-08-21 Size : 907kb User : emouse
jijiaqi Downloaded：0: Taxi meter, described the state of the actual taxi
Date : 2025-08-21 Size : 4kb User : luo
FPGA_PWM_ADS8364_STM32 Downloaded：0: FPGA Implementation of PWM, ADS8364 the parallel AD control, STM32 control the read and write operations source. Contains the complete project file.
Date : 2025-08-21 Size : 209kb User : emouse
fenpin3 Downloaded：0: 50 duty cycle of the waveform divided by simulation through
Date : 2025-08-21 Size : 155kb User : luo

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