VHDL-FPGA-Verilog List Page 1164

VHDL-FPGA-Verilog list

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05_UART_demo Downloaded：0: The UART instance EDK project is very simple and is mounted on the PLB bus the XPS-uartlite peripherals, general EDK works as a serial controller, the IP to use as a basic peripherals. Contains bit stream file downloaded
Date : 2025-08-21 Size : 887kb User : dujinzhe
cpu-risc Downloaded：0: wb_switch，opencore，risc cpu design。
Date : 2025-08-21 Size : 36kb User : 浮萍
wb_switch Downloaded：0: wb_switch，opencore，risc cpu design。
Date : 2025-08-21 Size : 2kb User : 浮萍
sw_leds Downloaded：0: wb_sw_leds，opencore，risc cpu design。
Date : 2025-08-21 Size : 1kb User : 浮萍
display-seg Downloaded：0: risc-cpu design，seg7，fpga
Date : 2025-08-21 Size : 2kb User : 浮萍
Yeni-WinRAR-archive Downloaded：0: vhdl defination beginning starter
Date : 2025-08-21 Size : 2kb User : xcfgvnhjkmlç
SPWM-output Downloaded：0: To utilize FPGA, generation of DDS technology with deadband control SPWM wave
Date : 2025-08-21 Size : 4.46mb User : yizhengxin
Lamp-from-left-to-right Downloaded：0: Then were lit in P0 port 8 LED from left to right cycle, resulting in a revolving door effect
Date : 2025-08-21 Size : 34kb User : 李先森
VHDL数学运算库 Downloaded：0: VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库VHDL数学运算库
Date : 2013-04-15 Size : 227.7kb User : 176995184@qq.com
Verilog Downloaded：0: the verilog syntax, hardware FPGA programming tools
Date : 2025-08-21 Size : 186kb User : 程三儿
lift Downloaded：0: Use VHDL to achieve controllable three elevator use of LED and dot matrix, said the elevator up and down the floor display
Date : 2025-08-21 Size : 308kb User : 张正宽
lab_3 Downloaded：0: The m sequence detection, " 1010" Verlog HDL, if there is a high output
Date : 2025-08-21 Size : 950kb User : 张正宽

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