wb_switch，opencore，risc cpu design。

rtl
...\altera
...\......\microcode.txt
...\defines.v
...\micro_rom.dat
...\modelsim.ini
...\rom_def.v
...\v86.v
...\v86_addsub.v
...\v86_alu.v
...\v86_alu.v.bak
...\v86_arlog.v
...\v86_bitlog.v
...\v86_conv.v
...\v86_core.v
...\v86_decode.v
...\v86_exec.v
...\v86_exec.v.bak
...\v86_fetch.v
...\v86_fulladd16.v
...\v86_jmp_cond.v
...\v86_memory_regs.v
...\v86_micro_data.v
...\v86_micro_rom.v
...\v86_mux8_1.v
...\v86_mux8_16.v
...\v86_next_or_not.v
...\v86_nstate.v
...\v86_opcode_deco.v
...\v86_othop.v
...\v86_regfile.v
...\v86_rxr16.v
...\v86_rxr8.v
...\v86_shrot.v
...\v86_wb_master.v

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