VHDL-FPGA-Verilog List Page 1126

VHDL-FPGA-Verilog list

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liushuideng Downloaded：0: failed to translate
Date : 2025-08-20 Size : 306kb User : vera
anjian-shumaguan-liushuideng Downloaded：0: failed to translate
Date : 2025-08-20 Size : 55kb User : vera
liushui Downloaded：0: failed to translate
Date : 2025-08-20 Size : 560kb User : 龙树东
3-8YIMAQI Downloaded：0: failed to translate
Date : 2025-08-20 Size : 206kb User : 龙树东
24xiaoshijishuqi Downloaded：0: Written in verilog 24 hour counter, which can be used as electronic clock, easy to understand.
Date : 2025-08-20 Size : 999kb User : 龙树东
JKchufaqi Downloaded：0: JK flip-flop based on FPGA, written in verilog, clear and simple, suitable for beginners.
Date : 2025-08-20 Size : 225kb User : 龙树东
BCD_adder Downloaded：0: Binary adder based on FPGA, simple, suitable for beginners to understand and accept it.
Date : 2025-08-20 Size : 719kb User : 龙树东
12864hanzixianshi Downloaded：0: 12864 liquid crystal display Chinese characters based on FPGA, written in verilog.
Date : 2025-08-20 Size : 390kb User : 龙树东
taxicounter Downloaded：0: Taxi meter based on CPLD, using VHDL language development, can realize the taxi meter simulation functions
Date : 2025-08-20 Size : 253kb User : 康国炼
ser Downloaded：0: FPGA serial-parallel converter. Including the Verilog source code and simulation waveform.
Date : 2025-08-20 Size : 275kb User : fc
mode3by3_generate_module Downloaded：1: failed to translate
Date : 2025-08-20 Size : 912kb User : 张皓
count_0 Downloaded：0: Continuous 16bits using the controller and data path in tervals of two between 1 and 0 of the largest number of counter. Including the top module, controller module and data channel module Verilog source code and simulat
Date : 2025-08-20 Size : 293kb User : fc

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