FPGA serial-parallel converter. Including the Verilog source code and simulation waveform.

ser\db\add_sub_q2i.tdf
...\..\ser.smp_dump.txt
...\..\ser_to_par.asm.qmsg
...\..\ser_to_par.asm_labs.ddb
...\..\ser_to_par.cbx.xml
...\..\ser_to_par.cmp.cdb
...\..\ser_to_par.cmp.hdb
...\..\ser_to_par.cmp.logdb
...\..\ser_to_par.cmp.qrpt
...\..\ser_to_par.cmp.rdb
...\..\ser_to_par.cmp.tdb
...\..\ser_to_par.cmp0.ddb
...\..\ser_to_par.dbp
...\..\ser_to_par.db_info
...\..\ser_to_par.eco.cdb
...\..\ser_to_par.eda.qmsg
...\..\ser_to_par.eds_overflow
...\..\ser_to_par.fit.qmsg
...\..\ser_to_par.fnsim.hdb
...\..\ser_to_par.fnsim.qmsg
...\..\ser_to_par.hier_info
...\..\ser_to_par.hif
...\..\ser_to_par.map.cdb
...\..\ser_to_par.map.hdb
...\..\ser_to_par.map.logdb
...\..\ser_to_par.map.qmsg
...\..\ser_to_par.pre_map.cdb
...\..\ser_to_par.pre_map.hdb
...\..\ser_to_par.psp
...\..\ser_to_par.rtlv.hdb
...\..\ser_to_par.rtlv_sg.cdb
...\..\ser_to_par.rtlv_sg_swap.cdb
...\..\ser_to_par.sgdiff.cdb
...\..\ser_to_par.sgdiff.hdb
...\..\ser_to_par.signalprobe.cdb
...\..\ser_to_par.sim.hdb
...\..\ser_to_par.sim.qmsg
...\..\ser_to_par.sim.qrpt
...\..\ser_to_par.sim.rdb
...\..\ser_to_par.sim.vwf
...\..\ser_to_par.sld_design_entry.sci
...\..\ser_to_par.sld_design_entry_dsc.sci
...\..\ser_to_par.syn_hier_info
...\..\ser_to_par.tan.qmsg
...\quartus_nativelink_simulation.log
...\ser.qpf
...\ser.qws
...\serv_req_info.txt
...\ser_to_par.asm.rpt
...\ser_to_par.done
...\ser_to_par.eda.rpt
...\ser_to_par.fit.eqn
...\ser_to_par.fit.rpt
...\ser_to_par.fit.summary
...\ser_to_par.flow.rpt
...\ser_to_par.map.eqn
...\ser_to_par.map.rpt
...\ser_to_par.map.summary
...\ser_to_par.pin
...\ser_to_par.pof
...\ser_to_par.qsf
...\ser_to_par.sim.rpt
...\ser_to_par.sof
...\ser_to_par.tan.rpt
...\ser_to_par.tan.summary
...\ser_to_par.v
...\ser_to_par.vwf
...\.imulation\modelsim\ser_to_par.vo
...\..........\........\ser_to_par.vt
...\..........\........\ser_to_par_modelsim.xrf
...\..........\........\ser_to_par_run_msim_gate_verilog.do
...\..........\........\ser_to_par_run_msim_gate_verilog.do.bak
...\..........\........\ser_to_par_run_msim_gate_verilog.do.bak1
...\..........\........\ser_to_par_v.sdo
...\..........\modelsim
...\db
...\simulation
ser

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