Continuous 16bits using the controller and data path in tervals of two between 1 and 0 of the largest number of counter. Including the top module, controller module and data channel module Verilog source code and simulation waveform.

count_0\controller.v
.......\count_0_num.asm.rpt
.......\count_0_num.done
.......\count_0_num.eda.rpt
.......\count_0_num.fit.eqn
.......\count_0_num.fit.rpt
.......\count_0_num.fit.summary
.......\count_0_num.flow.rpt
.......\count_0_num.map.eqn
.......\count_0_num.map.rpt
.......\count_0_num.map.summary
.......\count_0_num.pin
.......\count_0_num.pof
.......\count_0_num.qpf
.......\count_0_num.qsf
.......\count_0_num.qws
.......\count_0_num.sim.rpt
.......\count_0_num.sof
.......\count_0_num.tan.rpt
.......\count_0_num.tan.summary
.......\count_0_num.v
.......\count_0_num.vt
.......\count_0_num.vwf
.......\datapath.v
.......\.b\count_0_num.asm.qmsg
.......\..\count_0_num.asm_labs.ddb
.......\..\count_0_num.cbx.xml
.......\..\count_0_num.cmp.cdb
.......\..\count_0_num.cmp.hdb
.......\..\count_0_num.cmp.logdb
.......\..\count_0_num.cmp.qrpt
.......\..\count_0_num.cmp.rdb
.......\..\count_0_num.cmp.tdb
.......\..\count_0_num.cmp0.ddb
.......\..\count_0_num.dbp
.......\..\count_0_num.db_info
.......\..\count_0_num.eco.cdb
.......\..\count_0_num.eda.qmsg
.......\..\count_0_num.eds_overflow
.......\..\count_0_num.fit.qmsg
.......\..\count_0_num.hier_info
.......\..\count_0_num.hif
.......\..\count_0_num.map.cdb
.......\..\count_0_num.map.hdb
.......\..\count_0_num.map.logdb
.......\..\count_0_num.map.qmsg
.......\..\count_0_num.pre_map.cdb
.......\..\count_0_num.pre_map.hdb
.......\..\count_0_num.psp
.......\..\count_0_num.rtlv.hdb
.......\..\count_0_num.rtlv_sg.cdb
.......\..\count_0_num.rtlv_sg_swap.cdb
.......\..\count_0_num.sgdiff.cdb
.......\..\count_0_num.sgdiff.hdb
.......\..\count_0_num.signalprobe.cdb
.......\..\count_0_num.sim.hdb
.......\..\count_0_num.sim.qmsg
.......\..\count_0_num.sim.qrpt
.......\..\count_0_num.sim.rdb
.......\..\count_0_num.sim.vwf
.......\..\count_0_num.sld_design_entry.sci
.......\..\count_0_num.sld_design_entry_dsc.sci
.......\..\count_0_num.smp_dump.txt
.......\..\count_0_num.syn_hier_info
.......\..\count_0_num.tan.qmsg
.......\quartus_nativelink_simulation.log
.......\serv_req_info.txt
.......\.imulation\modelsim\count_0_num.vo
.......\..........\........\count_0_num.vt
.......\..........\........\count_0_num_modelsim.xrf
.......\..........\........\count_0_num_run_msim_gate_verilog.do
.......\..........\........\count_0_num_run_msim_gate_verilog.do.bak
.......\..........\........\count_0_num_run_msim_gate_verilog.do.bak1
.......\..........\........\count_0_num_run_msim_rtl_verilog.do
.......\..........\........\count_0_num_run_msim_rtl_verilog.do.bak
.......\..........\........\count_0_num_v.sdo
.......\timing\primetime\count_0_num.vo
.......\......\.........\count_0_num_pt_v.tcl
.......\......\.........\count_0_num_v.sdo
.......\simulation\modelsim
.......\timing\primetime
.......\db
.......\simulation
.......\timing
count_0

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