VHDL-FPGA-Verilog List Page 1067

VHDL-FPGA-Verilog list

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LED-xianshi---yimaqi Downloaded：0: 7-segment LED display decoder design using text input design method, by writing VHDL language program, complete the seven-segment LED display decoder design and timing simulation. 2, the design is completed to generate a
Date : 2025-08-14 Size : 53kb User : 杨帆
series_rxd_timing Downloaded：0: Receive asynchronous serial data, the data is written to the receiving fifo, you can set the timeout to receive multi-byte data, set the timeout period when the data does not appear, ready signal is valid, that receives
Date : 2025-08-14 Size : 5kb User : ppt555
UltraSensor-Vram-V8 Downloaded：0: FPGA Verilog language program, a serial port transceiver engine code, AD initialization acquisition code, the keyboard scan codes
Date : 2025-08-14 Size : 2.27mb User : guowuye
RAM_VHDL Downloaded：0: VHDL description of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
Date : 2025-08-14 Size : 1kb User : dengyaohui
MULTIPLICATER_AND_ADDER Downloaded：0: This procedure describes the implementation function y = ax+b (a and b are less than 1 8bit decimal) description of the hardware circuit, the final result just take the integer part, for the 8 bit output, and for roundin
Date : 2025-08-14 Size : 1kb User : dengyaohui
modelsim-run-one-step--Error- Downloaded：0: With modesim simulation run only when there will be a step not move, display " #** Error: (vsim-3601) Iteration limit reached at time 0 ps." Solution.
Date : 2025-08-14 Size : 6kb User : dengyaohui
CS5361_DAT Downloaded：0: CS5361 ADC drivers, of which there are clock parts, here is the data collection using VerilogHDL written, compiled in Libero using Actel chip test.
Date : 2025-08-14 Size : 1kb User : 王刚
keshe Downloaded：0: Perhaps a more useful digital dice. . After a random number and then the digital display
Date : 2025-08-14 Size : 23kb User : wang
lab4_project Downloaded：0: lab4 in ISE-based lab4 experimental program source code, here is the version ISE13.4
Date : 2025-08-14 Size : 2.75mb User : 周宏宽
RUILI Downloaded：0: Uniform phase Rayleigh fading channel matlab simulation program, together with detailed notes
Date : 2025-08-14 Size : 10kb User : 潘斯琦
3-8-decoder Downloaded：0: 3-8 decoder using Verilog HDL language description, including documentation and waveform capture
Date : 2025-08-14 Size : 16kb User : 孙璐
8-1-mux Downloaded：0: 8-1 MUX, Verilog HDL language description ， contains the file description and waveform capture
Date : 2025-08-14 Size : 15kb User : 孙璐

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