VHDL-FPGA-Verilog List Page 1071

VHDL-FPGA-Verilog list

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camera_test6 Downloaded：0: Camera data for 3* 3 forms processing and then median filter, 8 lines, fast
Date : 2025-08-14 Size : 8.62mb User : 朱腾飞
code Downloaded：0: 32bit ripple adder, 32bit CLA code
Date : 2025-08-14 Size : 9kb User : Leejs
TFT9325-SOPC-nios Downloaded：0: TFT9325 drive learning, based on nios source
Date : 2025-08-14 Size : 5.88mb User : mingbo
XS3S1000 Downloaded：0: XC3S1000FGG456 s program example
Date : 2025-08-14 Size : 1.93mb User : zyy
ln Downloaded：0: write vhdl natural logarithm, cordic iterate through the results. Improve the accuracy of the need to increase the number of iterations.
Date : 2025-08-14 Size : 1kb User : 叶韬
32678448can_IPCORE Downloaded：0: CAN bus IP core applications, more comprehensive, it is worth learning
Date : 2025-08-14 Size : 60kb User : 冰海情
keyboard Downloaded：0: VHDL a PS2 keyboard program to view some buttons on 7seg digit display
Date : 2025-08-14 Size : 253kb User : Pawel
a Downloaded：0: Function generator waveform by the waveform selector switch control output, respectively, can output square wave, triangle wave, sine wave
Date : 2025-08-14 Size : 19kb User : 张木月
led Downloaded：0: the led is flow water
Date : 2025-08-14 Size : 1kb User : 顾客
basys2 Downloaded：0: BASYS2 board, FPGA, to achieve M12 sequence generation and added to the low-frequency binary signal (input signal), and then to achieve the bit synchronization extraction.
Date : 2025-08-14 Size : 134kb User : 尹晨光
LCDIp Downloaded：0: A TFT-LCD driver of the IP core
Date : 2025-08-14 Size : 190kb User : 刘富伟
VHDL-book3 Downloaded：0: D_flipflop: 1-bit D flip-flop design D_fllipflop_behav: 4-bit D flip-flop design reg1bit: 1-bit register design reg4bit: 4-bit register design shiftreg4: general shift register design ring_shiftreg4: ring shift register
Date : 2025-08-14 Size : 8.6mb User : 贾诩

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