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vhdl译码显示器设计
Downloaded:0
VHDL decipher display design, written in quartus2 software, can realize the display and decoding function of the digital tube.
Date
: 2025-05-17
Size
: 7.32mb
User
:
YXT800
Rawski
Downloaded:0
two papers explains how to use fir filter by optimisation
Date
: 2025-05-17
Size
: 496kb
User
:
mamine2ia
LED_DISP
Downloaded:0
Input clock 4MHz, frequency division to 1Hz, clock count, LED display output, add enable EN and reset RST
Date
: 2025-05-17
Size
: 1.51mb
User
:
MmDawN
Hydrangeas
Downloaded:0
ferferf erferfref yhythy wedwefwefwefwefw grtgertegwerg
Date
: 2025-05-17
Size
: 579kb
User
:
haris_gr_blue
modelsim se 10.1a crack
Downloaded:0
Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses di
Date
: 2025-05-17
Size
: 511kb
User
:
冰激凌很牛
compterdiviseurfsm
Downloaded:0
FSM VHDL comportemental
Date
: 2025-05-17
Size
: 720kb
User
:
francois25
Lab4
Downloaded:0
The Booth multiplier is a better performance multiplier that is encoded and then computed Please try to describe the description 1. Booth multiplier principle Booth multiplier structure 3. And try to complete the Booth m
Date
: 2025-05-17
Size
: 67kb
User
:
dhfryytj
Ethernet_usd_send_quartus
Downloaded:0
Ethernet_UDP_send_quartus
Date
: 2025-05-17
Size
: 125kb
User
:
孤烟
vip_ex1
Downloaded:0
The routines on the privileged FPGA development board, the PLL initialization configuration and the LED light
Date
: 2025-05-17
Size
: 3.01mb
User
:
Ienovo
vip_ex2
Downloaded:0
The routines on the privileged students' development board, DDR2 controller integration and reading and writing tests
Date
: 2025-05-17
Size
: 538kb
User
:
Ienovo
counter
Downloaded:0
Add mode, subtraction, add and subtract mode, hold mode
Date
: 2025-05-17
Size
: 24kb
User
:
Coum
sdr_sdram
Downloaded:0
sdram verilog. SDRAM using interface simulation, Altera company IP use method
Date
: 2025-05-17
Size
: 12kb
User
:
风雪来
«
1
2
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.01
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106
.07
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4310
»
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