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VHDL-FPGA-Verilog list
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DAC_AD9708 verilog HDL code, AD9708 for top file, need to configure read only memory, output sine wave.
Date : 2025-05-17 Size : 3kb User : w74177

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A flow light program for FPGA.
Date : 2025-05-17 Size : 3.05mb User : Y_pricipal

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FPGA burn program to flash engineering example, the chip signal is EP4CE6F17C8N
Date : 2025-05-17 Size : 5.18mb User : Y_pricipal

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FPGA development board key process, the chip model is EP4CE6F17C8N
Date : 2025-05-17 Size : 5.11mb User : Y_pricipal

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FPGA development board key process, the chip model is EP4CE6F17C8N
Date : 2025-05-17 Size : 5.13mb User : Y_pricipal

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FPGAvga's use example, the chip model is EP4CE6F17C8N
Date : 2025-05-17 Size : 27.38mb User : Y_pricipal

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The read and write erasure commands of the serial flash communicate through the SPI interface. The CPU chip communicates with the FPGA through the SPI interface. Other functional integrated circuit chip parameters regist
Date : 2025-05-17 Size : 3.23mb User : 小云子

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It is used in FPGA development, written in VERILOG language, and simulated on the QUARTUS II simulation platform to realize the function of the frequency meter.
Date : 2025-05-17 Size : 363kb User : 丶静俟

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In accordance with the requirements of the logical analysis of the design and modeling of the digital baseband signal HDB3 decoder, HDB3 decoder principle, understand the logic function of each module circuit diagram, co
Date : 2025-05-17 Size : 8.57mb User : Remrinrin

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Date : 2025-05-17 Size : 3.17mb User : Dragonl

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Five level SVPWM pulse trigger program based on CPLD hardware description language
Date : 2025-05-17 Size : 327kb User : hurui

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Booth multiplier to implement the common Booth multiplication algorithm
Date : 2025-05-17 Size : 323kb User : 深蓝浅蓝eva
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