Embeded-SCM Develop List Page 792

Embeded-SCM Develop list

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sdr_sdram Downloaded：0: sdram verilog. SDRAM using interface simulation, Altera company IP use method
Date : 2025-06-28 Size : 12kb User : 风雪来
1-NRF24l01双向通信 Downloaded：0: NRF24L01 two-way communication
Date : 2025-06-28 Size : 31kb User : Pau1
1，STM32F4xx标准例程 Downloaded：0: STM32F4xx standard routine
Date : 2025-06-28 Size : 49.55mb User : iamwilson
DACAD9708 Downloaded：0: DAC_AD9708 verilog HDL code, AD9708 for top file, need to configure read only memory, output sine wave.
Date : 2025-06-28 Size : 3kb User : w74177
05 Downloaded：0: information on the basis of accuracy and smoothness. This process can be logically divided into two stagesIt is the activity of transforming one kind of language information into another kind of language
Date : 2025-06-28 Size : 15mb User : dfdfdfdflm
06 Downloaded：0: infor matione d into two stages on the basis of accurac y and smooth ness. This process can be logically divid
Date : 2025-06-28 Size : 4.52mb User : dfdfdfdflm
led Downloaded：0: A flow light program for FPGA.
Date : 2025-06-28 Size : 3.05mb User : Y_pricipal
02_run_flash_led Downloaded：0: FPGA burn program to flash engineering example, the chip signal is EP4CE6F17C8N
Date : 2025-06-28 Size : 5.18mb User : Y_pricipal
03_key_detect_1 Downloaded：0: FPGA development board key process, the chip model is EP4CE6F17C8N
Date : 2025-06-28 Size : 5.11mb User : Y_pricipal
04_key_detect_2 Downloaded：0: FPGA development board key process, the chip model is EP4CE6F17C8N
Date : 2025-06-28 Size : 5.13mb User : Y_pricipal
09_vga Downloaded：0: FPGAvga's use example, the chip model is EP4CE6F17C8N
Date : 2025-06-28 Size : 27.38mb User : Y_pricipal
智能交通灯程序 Downloaded：0: The traffic light time can be changed according to the human flow, and the efficiency of the traffic management system can be improved.
Date : 2025-06-28 Size : 45kb User : dznsd

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