Embeded-SCM Develop List Page 783

Embeded-SCM Develop list

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F1工程模板 Downloaded：0: Engineering template
Date : 2025-08-27 Size : 2.41mb User : 小敏敏123
carry_select adder_16-bit verilog Downloaded：0: this is code for carry_select adder_16-bit. written in verilog.
Date : 2018-01-12 Size : 743byte User : spgp1306
st75256 Downloaded：6: ST75256 driver, including SPI, 8080 interface reading and writing time series, based on 51 single chip test
Date : 2025-08-27 Size : 2kb User : YDP1990
Router fifo for NOC Downloaded：0: Router 8-bit fifo design, written in Verilog
Date : 2018-01-12 Size : 822byte User : spgp1306
Binarization verilog code Downloaded：0: Image processing binarisation verilog code
Date : 2018-01-12 Size : 308byte User : spgp1306
basic verilog codes Downloaded：0: Basic Verilog code includes RING and Johnson counters, Up-down counters, RAM, ROM, SIPO, PISO, SISO, PIPO, Mealy and Moore FSM codes
Date : 2018-01-12 Size : 9.17kb User : spgp1306
kogge stone adder VHDL code Downloaded：0: Generic kogge-stone adder and testbench IN VHDL
Date : 2018-01-12 Size : 218.36kb User : spgp1306
通用定时器(Timer) Downloaded：0: This is a few examples of general timer for ARM1138 development board, including 32 bit /16 bit single trigger timing, 32 bit /16 bit cycle timing /RTC timing, PWM application and so on.
Date : 2025-08-27 Size : 388kb User : 小芙
SPANNING TREE ADDER 27-bit VHDL Downloaded：0: 27-bit spanning tree adder written in VHDL coding
Date : 2018-01-12 Size : 185.53kb User : spgp1306
SPANING_27BIT Downloaded：0: spanning tree adder writtern vHDL Code
Date : 2025-08-27 Size : 185kb User : GIRISH
csa_codes Downloaded：0: carry_select_adder for 16-bit in verilog
Date : 2025-08-27 Size : 2kb User : GIRISH
频率脉冲可控，驱动步进电机 Downloaded：0: Using the interconnected timer, the step motor is controlled, the number and frequency of the measured pulse are controlled.
Date : 2025-08-27 Size : 2kb User : 安好琴天

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