Embeded-SCM Develop List Page 387

Embeded-SCM Develop list

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FP_adder Downloaded：0: 32 bit floating point adder with testbench
Date : 2025-06-07 Size : 11kb User : liki20
FP_divider Downloaded：0: floating point divider for 32 bit with test bench
Date : 2025-06-07 Size : 11kb User : liki20
FP_multiplier Downloaded：0: Multiplier for 32 bit with test bench using verilog HDL
Date : 2025-06-07 Size : 11kb User : liki20
PWN Downloaded：0: Pulse Width modulation using Verilog HDL
Date : 2025-06-07 Size : 6kb User : liki20
ADC_SA_8bit Downloaded：0: the successive approximation part of the circuit. trial_root is loaded with value 8'b1000_0000 on the rising egde that makes count = 3'b000.
Date : 2025-06-07 Size : 7kb User : liki20
4bit_mealy Downloaded：0: Mealy machine is a state machine whose output is determined by the current state and the current inputs.
Date : 2025-06-07 Size : 6kb User : liki20
4bit_moore Downloaded：0: Moore machine is state machine whose output is a function of only the current state.
Date : 2025-06-07 Size : 6kb User : liki20
HDL_equation Downloaded：0: Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
Date : 2025-06-07 Size : 5kb User : liki20
16_COMLEX ADDER Downloaded：0: Complex Numbers are denoted in the form a+ib where a is the real part and b is the imaginary part
Date : 2025-06-07 Size : 5kb User : liki20
miaobiao Downloaded：0: Write a python program to implement the stopwatch and clock function
Date : 2025-06-07 Size : 1kb User : ArsNova
4位全加器计数器等程序 Downloaded：0: EDA simulation tools used for EDA development of multiple programs; Including: 4 bit full adder, 12 frequency division, 128 frequency division, basketball counting stopwatch (part), counter; It can be used with EDA simul
Date : 2025-06-07 Size : 1kb User : 李云龙777
实验1计数显示器 Downloaded：0: Verify the function of the counter display
Date : 2025-06-07 Size : 38kb User : Canonoon

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