Embeded-SCM Develop List Page 2249

Embeded-SCM Develop list

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stm32 Downloaded：1: Used to learn STM32 based on the source code, connotation LED program, key program, system clock, watchdog, SPI-FLASH program (SST25VF016B), uart
Date : 2025-08-16 Size : 5.23mb User : 张鸿聪
SHORT_TRAINING Downloaded：0: Baseband OFDM communication system design based on XILINX FPGA module source of short training sequence
Date : 2025-08-16 Size : 198kb User : liu liushuai
chuankou Downloaded：0: Based on 51 single chip microcomputer serial communication code, serial port receives a signal, single chip microcomputer through a serial port to receive the original signal is sent out
Date : 2025-08-16 Size : 28kb User : liu liushuai
dp-51H1.tar Downloaded：0: Usb communication test source, ISP1581USB2.0 communication chip, to achieve faster than USB1.1 data communication. This procedure demonstrates that Example of sending and receiving communication using endpoint 1.
Date : 2025-08-16 Size : 207kb User : 张鸿聪
happybirthday Downloaded：0: SCM procedures, using SCM buzzer to play a happy birthday song
Date : 2025-08-16 Size : 2kb User : iio12345
chuankou-RS232 Downloaded：0: SCM procedures to achieve single-chip serial communication via RS232 interface
Date : 2025-08-16 Size : 61kb User : iio12345
ok_ir_24keys Downloaded：0: Elan MCU infrared remote control function
Date : 2025-08-16 Size : 6kb User : zzc
1602 Downloaded：0: Based on 51 single chip microcomputer LCD1602 program source code and LCD1602 data explanation in Chinese
Date : 2025-08-16 Size : 1.31mb User : liu liushuai
ex2 Downloaded：0: Based on NIOS II embedded development a minimum hardware system, software, download the test program test directly
Date : 2025-08-16 Size : 11.37mb User : liu liushuai
CCS5.5_CpuTimer0_RAM Downloaded：0: DSP2803 engineering instance documents, detailed tutorial and code, worth downloading
Date : 2025-08-16 Size : 3.73mb User : xuzhongyang
chufaqi Downloaded：0: This a a divider, written in Verilog division operation can be quickly
Date : 2025-08-16 Size : 1.11mb User : liu liushuai
dds Downloaded：0: This a use Verilog language implementation of a digital signal generator is presented
Date : 2025-08-16 Size : 2.61mb User : liu liushuai

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