Embeded-SCM Develop List Page 1572

Embeded-SCM Develop list

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stb_panel_fd650 Downloaded：0: displaymode : 8 segments and 4 chars segment drive current is not less than 25mA, char drive current is not less than 150 mA; 8 level luminunce control ; key scan :7*4bit high speed i2c internal crystal circuit internal
Date : 2025-09-19 Size : 6kb User : 鼻涕虫
315接收代码 Downloaded：0: 315M microcontroller based on stm32f0 receive code
Date : 2025-09-19 Size : 9.63mb User : Desprado
EX21_PWM Downloaded：0: pwm program for DSP2812
Date : 2025-09-19 Size : 843kb User : GUIMENG64
AD7689 Downloaded：0: AD7689 serial ADC, 12 bit, voltage type input, configurable internal reference Vref, very easy to use
Date : 2025-09-19 Size : 1kb User : ak0406
SHT10 Downloaded：0: SHT10 or SHT11 is integrated temperature and humidity sensor procedures, MCU is using STM32F103ZTE6, I used in outdoor equipment, after six months of operation, very stable
Date : 2025-09-19 Size : 3kb User : ak0406
DS3231 Downloaded：0: DS3231, ultra high precision, I2C bus simulation of STM32F103 control, I often use this chip in the project, driving after a long time of verification, should be vigorous
Date : 2025-09-19 Size : 2kb User : ak0406
HT1621B驱动程序 Downloaded：0: HT1621B LCD driver, including full screen light test, screen, write command, write data, write data in the specified address continuous function
Date : 2025-09-19 Size : 11kb User : L的笔记
Cortex-M3 技术参考手册-中文 Downloaded：0: Cortex-M3 kernel chip learning reference materials!
Date : 2025-09-19 Size : 1.35mb User : 精卫
stm32f412ve Downloaded：0: This is the STM32F412X series user programming data manual
Date : 2025-09-19 Size : 6.35mb User : 精卫
templates Downloaded：0: Nrf51822 MDK develops support for certain files, including protocol stacks
Date : 2025-09-19 Size : 16kb User : wgco
Firmware Downloaded：0: GCU firmware to implement USB, FPGA and TCP/IP protocols ~!
Date : 2025-09-19 Size : 1.58mb User : hudieysh
RS Downloaded：0: This paper is designed based on FPGA, described by Verilog HDL language in Galois field GF () on RS (6,4) encoder. Using the ISE software Verilog HDL language for each module is described, and then compile, simulation in
Date : 2025-09-19 Size : 3.68mb User : heyu7892020

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