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car Downloaded：0: Self-balancing robot walk upright Codes (effective pro-test), which stands upright on the car control and speed control (no direction control)
Date : 2026-01-17 Size : 10.82mb User : WXY
Jee-Reverse-Shows- Downloaded：0: Using thread reverse display the entered content
Date : 2026-01-17 Size : 7kb User : mlj
URAT Downloaded：0: In the ISE environment, using VHDL language RS232 serial port design, serial communication. Through the serial debugging tool to 0000000UART Send a hexadecimal number, FPGA serial data received by the UART converted to p
Date : 2026-01-17 Size : 394kb User : panda
Cartent Downloaded：0: Vehicle rental management system First, the project features: the design process, you can manage a variety of taxis and calculate their rent. Description: The main program management truck trucks, bus class Bus, Car Clas
Date : 2026-01-17 Size : 1kb User : 李鸿飞
count Downloaded：0: This experiment uses VHDL hardware description language to design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger Clock, the counter counts up, and the use of digital tube display, when the c
Date : 2026-01-17 Size : 464kb User : panda
MATLAB_PSpice_for_Electronic_Circuits_Ch5 Downloaded：0: MATLAB PSpice for Electronic Circuits Ch5
Date : 2026-01-17 Size : 4.36mb User : liu
HuaZhiApp28 Downloaded：0: blue tooth connect
Date : 2026-01-17 Size : 9.13mb User : weiqm
Papr-calculation-for-mc-cdma-system-using-rayleig Downloaded：0: Papr calculation for mc cdma system using rayleigh fading channel & awgn noise in matlab
Date : 2026-01-17 Size : 3kb User : liu
driver Downloaded：0: Basic configuration and development of STM32 motor. Basically meet the PWM control motor
Date : 2026-01-17 Size : 2kb User : 犀牛
Gps-receiver-using-xilinx-fpga-and-ti-dsp-in-matl Downloaded：0: Gps receiver using xilinx fpga and ti dsp in matlab
Date : 2026-01-17 Size : 3.08mb User : liu
A Downloaded：0: Combined with VB, GPS, through programming on the coordinates of the positive and negative calculation as well as network adjustment
Date : 2026-01-17 Size : 83kb User : QLN
up_counter_8 Downloaded：0: Code for 8bit up counter in Verilog
Date : 2026-01-17 Size : 42kb User : zsan

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