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Firefly_test Downloaded：0: Artificial intelligence swarm optimization algorithm test code
Date : 2025-07-24 Size : 1kb User : None
sin_en Downloaded：0: DDS by the phase increment, phase accumulator, quantizer and sine and cosine lookup table of four parts. The phase accumulator accumulates a fixed phase value for each period, and then finds the corresponding value the l
Date : 2025-07-24 Size : 2.59mb User : panda
clock Downloaded：0: VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes, To achieve the increase or decrease minutes. The design includes the following sections: (1
Date : 2025-07-24 Size : 484kb User : panda
MoblieSafe Downloaded：0: Andrews development, imitation mobile guards, a little bug
Date : 2025-07-24 Size : 30.57mb User : 高国明
TrafficSign Downloaded：0: codeblocks Linux Traffic sign recognition
Date : 2025-07-24 Size : 16.6mb User : 朱仁杰
Fibonacci Downloaded：0: (1) clkdiv module: the 50MHz system clock frequency, were 190Hz, 3Hz signal. The 190 Hz signal is used to dynamically scan the module bit signal and the 3 Hz signal is used for the fib module. (2) fib module: According t
Date : 2025-07-24 Size : 652kb User : panda
car Downloaded：0: Self-balancing robot walk upright Codes (effective pro-test), which stands upright on the car control and speed control (no direction control)
Date : 2025-07-24 Size : 10.82mb User : WXY
Jee-Reverse-Shows- Downloaded：0: Using thread reverse display the entered content
Date : 2025-07-24 Size : 7kb User : mlj
URAT Downloaded：0: In the ISE environment, using VHDL language RS232 serial port design, serial communication. Through the serial debugging tool to 0000000UART Send a hexadecimal number, FPGA serial data received by the UART converted to p
Date : 2025-07-24 Size : 394kb User : panda
Cartent Downloaded：0: Vehicle rental management system First, the project features: the design process, you can manage a variety of taxis and calculate their rent. Description: The main program management truck trucks, bus class Bus, Car Clas
Date : 2025-07-24 Size : 1kb User : 李鸿飞
count Downloaded：0: This experiment uses VHDL hardware description language to design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger Clock, the counter counts up, and the use of digital tube display, when the c
Date : 2025-07-24 Size : 464kb User : panda
MATLAB_PSpice_for_Electronic_Circuits_Ch5 Downloaded：0: MATLAB PSpice for Electronic Circuits Ch5
Date : 2025-07-24 Size : 4.36mb User : liu

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