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Src2 Downloaded：1: Attitude Determination and Control system Software for UPSat
Date : 2026-01-17 Size : 7kb User : Phito
VGA_disp Downloaded：0: Clk divid module for the frequency circuit, the 50MHz system clock frequency to produce 50M/7Hz pixel clock. VGA control module for the VGA display control circuit module, driven by the pixel clock in the first line-freq
Date : 2026-01-17 Size : 1.2mb User : panda
placeUErand Downloaded：0: Cellular network UE rand distribution
Date : 2026-01-17 Size : 5kb User : None
placeUEsingle Downloaded：0: Cellular network single UE distribution
Date : 2026-01-17 Size : 1kb User : None
traffic-light Downloaded：0: (1) Divid module: 1Hz divider module, the development board provides 50MHz system clock, and the design of traffic lights Conversion in seconds for the time unit, the 50MHz frequency to be 1Hz pulse signal. (2) Divid_200
Date : 2026-01-17 Size : 521kb User : panda
placeUEuni Downloaded：0: Cellular network UE uniform distribution
Date : 2026-01-17 Size : 1kb User : None
Firefly_test Downloaded：0: Artificial intelligence swarm optimization algorithm test code
Date : 2026-01-17 Size : 1kb User : None
sin_en Downloaded：0: DDS by the phase increment, phase accumulator, quantizer and sine and cosine lookup table of four parts. The phase accumulator accumulates a fixed phase value for each period, and then finds the corresponding value the l
Date : 2026-01-17 Size : 2.59mb User : panda
clock Downloaded：0: VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes, To achieve the increase or decrease minutes. The design includes the following sections: (1
Date : 2026-01-17 Size : 484kb User : panda
MoblieSafe Downloaded：0: Andrews development, imitation mobile guards, a little bug
Date : 2026-01-17 Size : 30.57mb User : 高国明
TrafficSign Downloaded：0: codeblocks Linux Traffic sign recognition
Date : 2026-01-17 Size : 16.6mb User : 朱仁杰
Fibonacci Downloaded：0: (1) clkdiv module: the 50MHz system clock frequency, were 190Hz, 3Hz signal. The 190 Hz signal is used to dynamically scan the module bit signal and the 3 Hz signal is used for the fib module. (2) fib module: According t
Date : 2026-01-17 Size : 652kb User : panda

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