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[VHDL-FPGA-Verilog] vhdl_vga

Description: 彩条信号发生器使用说明 使用模块有：VGA接口、脉冲沿模块、时钟源模块。 使用步骤： 1. 打开电源+5V 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载。 4. 将彩色显示器的线与VGA接口连接好。 5. 彩条信号就可以在显示器中产生，通过脉冲沿模块按键MS1可以改变产生彩条的 -color of the signal generator for use with the use of modules : VGA, pulse along the module, module clock source. Use steps : 1. Turn the power 5V 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connections and will be loading procedures. 4. Will the line color display with VGA interface connector good. 5. Choi of the signal can be generated in the display, along the pulse button MS1 module can change color of the produce
Platform: | Size: 95232 | Author: 刘浪 | Hits:

[VHDL-FPGA-Verilog] VGA_Clock

Description: 基于spartan3火龙刀系列FPGA开发板制作的VGA实验例程-Fire Dragon spartan3 knife series based FPGA development board VGA produced experimental routines
Platform: | Size: 10240 | Author: 朱东亮 | Hits:

[VHDL-FPGA-Verilog] Final

Description: many application on kit SP-3: VGA, digital clock, counter, interface PS2-many application on kit SP-3: VGA, digital clock, counter, interface PS2....
Platform: | Size: 50176 | Author: nguyen hung | Hits:

[VHDL-FPGA-Verilog] vgaclock

Description: vga显示的数字时钟,用mif文件实现，用以大家学习交流-vga display digital clock, with the realization of mif file for them to learn from the exchange of
Platform: | Size: 51200 | Author: jichun | Hits:

[2D Graphic] yavga

Description: This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable charset (you can use a simple text editor in order to "visually" customize it) * It can display a color "waveform" * It can display a color grid and "cross cursor" -This core is a simple and small VGA controller. * It drives vga monitors with an 800x600 resolution and 72Hz vertical refresh rate (50MHz pixel clock) * It displays chars on the screen (each char is 8x16 pixels) * It has a customizable charset (you can use a simple text editor in order to "visually" customize it) * It can display a color "waveform" * It can display a color grid and "cross cursor"
Platform: | Size: 44032 | Author: sdroamt | Hits:

[VHDL-FPGA-Verilog] VGA_v

Description: 基于 FPGA 的VGA显示控制器设计（采用Verilog 语言） 控制VGA显示模块 VGA_HS,VGA_VS1,VGA_BLANK时序的发生器。包括测试程序 采用ALTERA Cyclone II系列芯片EP2C8Q208C8N芯片测试成功。-module VGA(CLK_50,RST_N,VGA_HS,VGA_VS1,VGA_BLANK, VGA_CLK,VGA_SYNC,VGA_R,VGA_G,VGA_B) input CLK_50 input RST_N //////////////////////// VGA //////////////////////////// output VGA_CLK // VGA Clock output VGA_HS // VGA H_SYNC output VGA_VS1 // VGA V_SYNC output VGA_BLANK // VGA BLANK output VGA_SYNC // VGA SYNC output [9:0] VGA_R // VGA Red[9:0] output [9:0] VGA_G // VGA Green[9:0] output [9:0] VGA_B // VGA Blue[9:0]
Platform: | Size: 520192 | Author: 林锦鸿 | Hits:

[Other] vga1

Description: VGA显示源码，行信号，场信号和时钟模块-VGA display source code, line signals, market signals and clock modules
Platform: | Size: 7168 | Author: 郭大狗 | Hits:

[VHDL-FPGA-Verilog] vga

Description: SPARTAN3AN VGA test it s for starters to get the idea about how to use vga port on spartan3an kit. in this code , first 50mhz clock used to create a 25 mhz clock to use in vga snchronization . then a simple window is created on the screen -SPARTAN3AN VGA test it s for starters to get the idea about how to use vga port on spartan3an kit. in this code , first 50mhz clock used to create a 25 mhz clock to use in vga snchronization . then a simple window is created on the screen
Platform: | Size: 1024 | Author: gasd | Hits:

[VHDL-FPGA-Verilog] VGA2

Description: VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
Platform: | Size: 2048 | Author: alzemiro | Hits:

[Other Embeded program] VGA_ATMega48

Description: VGA clock with ATMega48 (20MHz crystal, 800x600@60Hz)
Platform: | Size: 2048 | Author: Szombi | Hits:

[VHDL-FPGA-Verilog] vga

Description: 基于QuartusII 6.0 环境的vga驱动程序，所用芯片为EP1C6Q240C8,开发板时钟50M，显示模式800*600，72Hz，内容是在频幕显示几条直线。-Environment based on QuartusII 6.0 vga drivers, the chips for the EP1C6Q240C8, development board clock 50M, the display mode 800* 600,72 Hz, the frequency content of screen displays several lines.
Platform: | Size: 220160 | Author: x_metal | Hits:

[VHDL-FPGA-Verilog] clock

Description: 一个简单的FPGA时钟，里面有PDF说明~-A simple clock sample. There exists a PDF statement files in it. If there exists any problem please contact me.
Platform: | Size: 21504 | Author: chobits | Hits:

[VHDL-FPGA-Verilog] vhdl-clock-with-vga-output-for-Nexys-2

Description: Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.
Platform: | Size: 28672 | Author: hatsjoe | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 实现vga的实现odule VGA( clock, switch, disp_RGB, hsync, vsync ) input clock //系统输入时钟 50MHz input [1:0]switch output [2:0]disp_RGB //VGA数据输出 output hsync //VGA行同步信号 output vsync //VGA场同步信号 reg [9:0] hcount //VGA行扫描计数器 reg [9:0] vcount //VGA场扫描计数器 reg [2:0] data reg [2:0] h_dat reg [2:0] v_dat //reg [9:0] timer reg flag wire hcount_ov wire vcount_ov wire dat_act wire hsync wire vsync reg vga_clk //VGA行、场扫描时序参数表-Vga achieve the realization odule VGA (clock, switch, disp_RGB, hsync, vsync) input clock // system input clock 50MHz input [1:0] switch output [2:0] disp_RGB // VGA output hsync data output // VGA horizontal synchronization signal output vsync // VGA vertical sync signals reg [9:0] hcount // VGA line scan counter reg [9:0] vcount // VGA-field scanning counter reg [2:0] data reg [2:0] h_dat reg [2:0] v_dat // reg [9:0] timer reg flag wire hcount_ov wire vcount_ov wire dat_act wire hsync wire vsync reg vga_clk // VGA horizontal and vertical scanning Timing Parameters Table
Platform: | Size: 45056 | Author: 李阳 | Hits:

[VHDL-FPGA-Verilog] vga

Description: vga This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.-This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.
Platform: | Size: 219136 | Author: jiang nan | Hits:

[VHDL-FPGA-Verilog] vga_driver

Description: 基于EP3C16的VGA显示驱动工程。时钟40M，图片存储在FPGA内部的ROM中，VGA显示器分辨力为800*600*60Hz，存储图片需要800*600点（bit），由于EP3C16的ROM不够大，ROM中存储内容为8bit*30000；显示器内容为上下半屏分别显示ROM中的内容，显示图片相同。ROM中的内容由地址线的变化来控制。-Display driver works based EP3C16 of VGA. Clock 40M, pictures stored in the ROM of the FPGA, VGA display resolution is 800* 600* 60Hz, store pictures need 800* 600 (bit), due to EP3C16 the ROM is not big enough, ROM for storing the contents of 8bit* 30000 monitor content for the upper and lower half of the screen show the ROM content, display the same picture. ROM are controlled by the change in the address line.
Platform: | Size: 11255808 | Author: 郭俊媛 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: FPGA控制VGA显示Verilog程序代码，VGA显示8钟色彩条和网络方格-FPGA Verilog code control VGA display, VGA display 8 clock color bar and network grid
Platform: | Size: 3335168 | Author: 刘先生 | Hits:

[VHDL-FPGA-Verilog] AD9883 iic_v1.0_for_sim

Description: 程序用于配置AD9883芯片寄存器，采用iic协议。 FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Processing Sync Detect for Hot Plugging Midscale Clamping Power-Down Mode Low Power: 500 mW Typical 4:2:2 Output Format Mode APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV(Program used to configure the AD9883 chip register, using the IIC protocol.)
Platform: | Size: 4934656 | Author: kilyc | Hits:

[VHDL-FPGA-Verilog] vga_7_0728

Description: 用vga显示数字钟，通过串口可以控制时间显示(With vga digital clock, through the serial port can control the time display)
Platform: | Size: 12918784 | Author: wuyezhiyue | Hits:

[VHDL-FPGA-Verilog] 秒表

Description: 秒表,vga显示，可修改时间，可设置闹钟(The stopwatch, VGA display, can modify the time, can set the alarm clock)
Platform: | Size: 2712576 | Author: 小二郎儿 | Hits:
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