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[Other resourcemicro uart

Description: 硬件uart源程序verilog HDL,即相关文档-hardware UART Verilog HDL source, that the relevant documents
Platform: | Size: 342886 | Author: 陈正一 | Hits:

[Com Portuartok

Description: 采用verilog编写的串口通信程序,采用了状态机设计!程序简单,消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few.
Platform: | Size: 431104 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilogmicro uart

Description: 硬件uart源程序verilog HDL,即相关文档-hardware UART Verilog HDL source, that the relevant documents
Platform: | Size: 343040 | Author: 陈正一 | Hits:

[Com Portverilog_UART

Description: UART verilog hdl 实现-UART Verilog HDL achieve
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-VerilogAltera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[Otheruartvhrilog

Description: This Verilog HDL description implements a UART.
Platform: | Size: 3072 | Author: chenhe | Hits:

[VHDL-FPGA-Veriloguartverlog

Description: 占用资源少的verilog HDL uart接口;采用固定波特率115200,可以修改程序中的分频来修改波特率,模式为1个启始位,8位数据位,1个停止位;带1字节缓存;当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[Other Embeded programuart

Description: 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.-Simple UART functions in the compiler under QUARTUS4.0 through using VERILOG HDL preparation.
Platform: | Size: 1024 | Author: 不是 | Hits:

[Com Portuart2iic

Description: UART转I2C的Verilog HDL代码,由北京邮电大学《VerilogHDL设计与EDA技术基础》教师编写-UART to I2C of the Verilog HDL code, by the Beijing University of Posts and Telecommunications VerilogHDL design and EDA technology infrastructure Teacher preparation
Platform: | Size: 3072 | Author: emulous | Hits:

[Com Portrec

Description: uart串口通信程序 用VERILOG HDL 编写 可以有效应用于FPGA上-UART serial communication program with VERILOG HDL can be effectively used in the preparation of the FPGA
Platform: | Size: 1024 | Author: 德刚 | Hits:

[VHDL-FPGA-VerilogFusion_UART

Description: UART实验Verilog HDL代码,用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilogverilog_UART

Description: This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
Platform: | Size: 3072 | Author: keyoung | Hits:

[VHDL-FPGA-Veriloguart_0

Description: 异步串行通信Uart接口设计,Verilog HDL程序,嵌入式必备哦-Asynchronous serial communication UART Interface Design, Verilog HDL procedures essential embedded Oh
Platform: | Size: 5120 | Author: 白雪 | Hits:

[VHDL-FPGA-VerilogUART_send

Description: Verilog HDL 串口发送程序,在ACTEL Fusion FPGA上实验成功 ,和大家一起分享!^_^-Verilog HDL send serial procedures, ACTEL Fusion FPGA in the success of the experiment, and share with everyone! ^ _ ^
Platform: | Size: 1024 | Author: whq | Hits:

[VHDL-FPGA-VerilogUART

Description: 串口实验,很好用,我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Platform: | Size: 338944 | Author: 韩思贤 | Hits:

[VHDL-FPGA-Veriloguart

Description: uart using verilog hdl
Platform: | Size: 12288 | Author: imran ahmed | Hits:

[Otheruart_rx

Description: Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language) code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-VerilogUART

Description: FPGA的UART程序,非常好的,讲解详细,我当初看了好多都看不懂,看了这个以后终于明白-FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this
Platform: | Size: 276480 | Author: xuxing | Hits:

[VHDL-FPGA-VerilogUART

Description: Verilog HDL写的实现UART收发程序-Realization of Verilog HDL UART receive written procedures
Platform: | Size: 709632 | Author: xiong | Hits:

[VHDL-FPGA-VerilogVerilog-HDL

Description: Verilog HDL设计+Modelsim仿真UART-Verilog HDL Designing+ Modelsim UART simulation
Platform: | Size: 23552 | Author: WangQunfeng | Hits:
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