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[Other resource] wishbone_i2c_master

Description: -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core -- -- author : Richard Herveille -- rev. 0.1 based on simple_i 2c -- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman) -- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt -
Platform: | Size: 5470 | Author: 郑开科 | Hits:

[Com Port] wishbone_i2c_master_vhd

Description: WISHBONE revB2 compiant I2C master core
Platform: | Size: 5807 | Author: weixing | Hits:

[VHDL-FPGA-Verilog] wishbone_i2c_master

Description: -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
Platform: | Size: 5120 | Author: 郑开科 | Hits:

[VHDL-FPGA-Verilog] i2c_slave_model_verilog

Description: 一般网站上都有i2c master模块的代码,但很少有slave的代码,这里就是slave的代码,非常有用.-general website have i2c master module of code, but very few slave code, This is the slave code, very useful.
Platform: | Size: 2048 | Author: hxwf801 | Hits:

[Com Port] wishbone_i2c_master_vhd

Description: WISHBONE revB2 compiant I2C master core
Platform: | Size: 5120 | Author: weixing | Hits:

[VC/MFC] altera_avalon_i2c

Description: i2c IP核 i2c.master i2c.mater.v-i2c IP core
Platform: | Size: 181248 | Author: zhengzhiqiang | Hits:

[Embeded-SCM Develop] i2c_core

Description: I2C core 及testbench（verilog）-I2C core and testbench [verilog]
Platform: | Size: 20480 | Author: xiaoheng | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core

Description: I2C master/slave IP core
Platform: | Size: 2180096 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[VHDL-FPGA-Verilog] I2C-Master-_-Slave-Core

Description: 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程-Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming
Platform: | Size: 2181120 | Author: 郭天然 | Hits:

[SCM] i2c_latest[1].tar

Description: I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus.
Platform: | Size: 1479680 | Author: zhong | Hits:

[VHDL-FPGA-Verilog] i2c_master_slave_core_latest.tar

Description: This design is Wishbone compatible I2C core. This core can work as I2C master as well as slave. VMM Test-bench is also available.
Platform: | Size: 4562944 | Author: Andrey | Hits:

[VHDL-FPGA-Verilog] i2c

Description: 这是一个 OPENCORES的I2C MASTER CORE,非常实用-This is a core from opencores,and it is very useful
Platform: | Size: 1521664 | Author: zhangchao | Hits:

[VHDL-FPGA-Verilog] i2c_master_byte_ctrl

Description: i2c core : i2c master byte control
Platform: | Size: 3072 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] i2c_master_top

Description: i2c core : i2c master top
Platform: | Size: 4096 | Author: cuong | Hits:

[VHDL-FPGA-Verilog] i2c

Description: I2C master mode IP core
Platform: | Size: 276480 | Author: Liu Zhao | Hits:

[VHDL-FPGA-Verilog] Nios-II-I2C

Description: 使用开源的IIC MASTER Core，将它加载到NIOSII的AVALON总线上，这样对于NIOSII控制器而言，IIC MASTER就是一个硬件实现的控制器，用户通过调用API函数就能很容易的对IIC进行操作，而且IIC的运行并不占用NIOSII软核宝贵的资源和时间。 -Open source IIC MASTER Core,it is loaded into the AVALON bus NIOSII This NIOSII controller,IIC MASTER is a hardware implementation of the controller,the user by calling the API function can easily IIC operation IIC operation does not take up valuable resources and time NIOSII soft core.
Platform: | Size: 13507584 | Author: 朱媛 | Hits:

[VHDL-FPGA-Verilog] i2c_latest.tar

Description: i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus. It is an easy path to add I2C capabilities to any Wishbone compatible system. You can find the I2C specifications on Phillips web Site. Work was originally started by Frédéric Renet.
Platform: | Size: 1479680 | Author: | Hits:

[Linux-Unix] i2c-designware-core

Description: Synopsys DesignWare I2C adapter driver (master only).
Platform: | Size: 8192 | Author: ginkenqing | Hits:

[Linux-Unix] i2c-designware-core

Description: Synopsys DesignWare I2C adapter driver (master only).
Platform: | Size: 8192 | Author: jangcongbm | Hits:
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