Description: -- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
- [Wishbone] - wishbone bus protocol detailed technical
- [i2c_code(VHDL).Rar] - i2c source VHDL language, communicating
- [tst_ds1621] - -- State machine for reading data from D
- [dcjzqn] - in Turbo C development environment and a
- [i2c_master] - Avalon I2C master. Ready to use with SOP
- [wishbone_i2c_master_vhd] - WISHBONE revB2 compiant I2C master core
- [hough] - Good image processing source code, put t
- [OnItFirewall] - Procedures for full-featured very profes
- [wb_rtc] - //-*- Mode: Verilog-*- // Filename : wb_
- [uart] - UART protocol, implementation, verificat
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