bench
.....\i2c_slave_model.v
.....\spi_slave_model.v
.....\tst_bench_top.v
.....\wb_master_model.v
verilog
.......\i2c_master_bit_ctrl.v
.......\i2c_master_byte_ctrl.v
.......\i2c_master_defines.v
.......\i2c_master_top.v
.......\timescale.v